[llvm] 3ee96a2 - [AArch64] Add SME 2 target feature for Armv8-A and Armv9-A 2022 Architecture Extension
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 13 03:40:09 PDT 2022
Author: Caroline Concatto
Date: 2022-10-13T11:28:08+01:00
New Revision: 3ee96a26d59d57867a270ee82f16c3a36947a4fb
URL: https://github.com/llvm/llvm-project/commit/3ee96a26d59d57867a270ee82f16c3a36947a4fb
DIFF: https://github.com/llvm/llvm-project/commit/3ee96a26d59d57867a270ee82f16c3a36947a4fb.diff
LOG: [AArch64] Add SME 2 target feature for Armv8-A and Armv9-A 2022 Architecture Extension
First patch in a series adding MC layer support for Scalable Matrix
Extension 2 (SME2).
This patch adds the following feature:
sme2
The 2022 Architecture Extension release adds other feature flags(eg.:sme2.1),
that will be in follow-up patches.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D135448
Added:
llvm/test/MC/AArch64/SME2/feature-sme2-implies-sme.s
Modified:
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SchedA64FX.td
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index 3dae2ac159fb5..b0745c3130834 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -146,6 +146,7 @@ AARCH64_ARCH_EXT_NAME("flagm", AArch64::AEK_FLAGM, "+flagm",
AARCH64_ARCH_EXT_NAME("sme", AArch64::AEK_SME, "+sme", "-sme")
AARCH64_ARCH_EXT_NAME("sme-f64", AArch64::AEK_SMEF64, "+sme-f64", "-sme-f64")
AARCH64_ARCH_EXT_NAME("sme-i64", AArch64::AEK_SMEI64, "+sme-i64", "-sme-i64")
+AARCH64_ARCH_EXT_NAME("sme2", AArch64::AEK_SME2, "+sme2", "-sme2")
AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC, "+hbc", "-hbc")
AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops")
AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon")
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h
index 1065b858ab5d0..acc32341c8d39 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -72,6 +72,7 @@ enum ArchExtKind : uint64_t {
AEK_HBC = 1ULL << 40, // FEAT_HBC
AEK_MOPS = 1ULL << 41, // FEAT_MOPS
AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3
+ AEK_SME2 = 1ULL << 43, // FEAT_SME2
};
enum class ArchKind {
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 51a8f957a96bd..efe0f9be9f044 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -473,6 +473,9 @@ def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
"Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
+def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
+ "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
+
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
"Apple A7 (the CPU formerly known as Cyclone)">;
@@ -642,7 +645,7 @@ def PAUnsupported : AArch64Unsupported {
}
def SMEUnsupported : AArch64Unsupported {
- let F = [HasSME, HasSMEF64, HasSMEI64];
+ let F = [HasSME, HasSMEF64, HasSMEI64, HasSME2];
}
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e7da8238db05a..fab471aa15428 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -142,6 +142,8 @@ def HasSMEF64 : Predicate<"Subtarget->hasSMEF64()">,
AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">;
def HasSMEI64 : Predicate<"Subtarget->hasSMEI64()">,
AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">;
+def HasSME2 : Predicate<"Subtarget->hasSME2()">,
+ AssemblerPredicate<(all_of FeatureSME2), "sme2">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
def HasSVEorSME
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 8b0b84497180a..dec56e7f8d38e 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -22,7 +22,7 @@ def A64FXModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures =
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
- HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16];
+ HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2];
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 5b1e9b5bcf23e..b7d337dfa76dc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -26,6 +26,7 @@ def ThunderX3T110Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
+ SMEUnsupported.F,
[HasMTE]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
diff --git a/llvm/test/MC/AArch64/SME2/feature-sme2-implies-sme.s b/llvm/test/MC/AArch64/SME2/feature-sme2-implies-sme.s
new file mode 100644
index 0000000000000..290da41ee3e19
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/feature-sme2-implies-sme.s
@@ -0,0 +1,8 @@
+// This test verifies SME2 implies SME.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s \
+// RUN: | FileCheck %s
+
+addha za0.s, p0/m, p0/m, z0.s
+// CHECK-NOT: instruction requires: sme
+// CHECK: addha za0.s, p0/m, p0/m, z0.s
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 06008ee0f2645..4308d250cc9cf 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1504,7 +1504,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64, AArch64::AEK_SMEI64,
- AArch64::AEK_HBC, AArch64::AEK_MOPS, AArch64::AEK_PERFMON};
+ AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
+ AArch64::AEK_PERFMON};
std::vector<StringRef> Features;
@@ -1561,6 +1562,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sme"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-i64"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sme2"));
EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
@@ -1639,6 +1641,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sme", "nosme", "+sme", "-sme"},
{"sme-f64", "nosme-f64", "+sme-f64", "-sme-f64"},
{"sme-i64", "nosme-i64", "+sme-i64", "-sme-i64"},
+ {"sme2", "nosme2", "+sme2", "-sme2"},
{"hbc", "nohbc", "+hbc", "-hbc"},
{"mops", "nomops", "+mops", "-mops"},
{"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
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