[llvm] 7d15212 - [ARM] Support fp16/bf16 using w constraint

[Archibald Elliott via llvm-commits]

Author: Archibald Elliott
Date: 2022-10-13T10:32:06+01:00
New Revision: 7d15212b8c0c8bf0009ab253e7179ae7caf57aec

URL: https://github.com/llvm/llvm-project/commit/7d15212b8c0c8bf0009ab253e7179ae7caf57aec
DIFF: https://github.com/llvm/llvm-project/commit/7d15212b8c0c8bf0009ab253e7179ae7caf57aec.diff

LOG: [ARM] Support fp16/bf16 using w constraint

fp16 and bf16 values can be used in GCC's inline assembly using the "w"
constraint, which means "VFP floating-point registers d0-d31" - fp16 and
bf16 values are stored in S registers (which alias the D registers).

This change ensures that LLVM is compatible with GCC for programs that
use fp16 and the 'w' constraint.

Differential Revision: https://reviews.llvm.org/D135662

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp
    llvm/test/CodeGen/ARM/inlineasm-fp-half.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cb46201f0b992..ccfcd89a64403 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20141,6 +20141,8 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
     case 'w':
       if (VT == MVT::Other)
         break;
+      if (VT == MVT::f16 || VT == MVT::bf16)
+        return RCPair(0U, &ARM::HPRRegClass);
       if (VT == MVT::f32)
         return RCPair(0U, &ARM::SPRRegClass);
       if (VT.getSizeInBits() == 64)

diff  --git a/llvm/test/CodeGen/ARM/inlineasm-fp-half.ll b/llvm/test/CodeGen/ARM/inlineasm-fp-half.ll
index b2a894f49c52e..6da247795a3f6 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-fp-half.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-fp-half.ll
@@ -3,8 +3,8 @@
 ; RUN: llc -mtriple=thumb -mattr=+armv8.2-a,+fp-armv8,+fullfp16,+bf16,-neon %s -o - | FileCheck %s
 
 
-define arm_aapcscc half @f(half %x) nounwind {
-; CHECK-LABEL: f:
+define arm_aapcscc half @f_t(half %x) nounwind {
+; CHECK-LABEL: f_t:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.f16 s0, r0
 ; CHECK-NEXT:    @APP
@@ -17,8 +17,22 @@ entry:
   ret half %0
 }
 
-define arm_aapcscc bfloat @h(bfloat %x) nounwind {
-; CHECK-LABEL: h:
+define arm_aapcscc half @f_w(half %x) nounwind {
+; CHECK-LABEL: f_w:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.f16 s0, r0
+; CHECK-NEXT:    @APP
+; CHECK-NEXT:    vsqrt.f16 s0, s0
+; CHECK-NEXT:    @NO_APP
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call half asm "vsqrt.f16 $0, $1", "=w,w"(half %x)
+  ret half %0
+}
+
+define arm_aapcscc bfloat @h_t(bfloat %x) nounwind {
+; CHECK-LABEL: h_t:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.f16 s0, r0
 ; CHECK-NEXT:    @APP
@@ -30,3 +44,17 @@ entry:
   %0 = tail call bfloat asm "vmov.f32 $0, $1", "=t,t"(bfloat %x)
   ret bfloat %0
 }
+
+define arm_aapcscc bfloat @h_w(bfloat %x) nounwind {
+; CHECK-LABEL: h_w:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.f16 s0, r0
+; CHECK-NEXT:    @APP
+; CHECK-NEXT:    vmov.f32 s0, s0
+; CHECK-NEXT:    @NO_APP
+; CHECK-NEXT:    vmov.f16 r0, s0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call bfloat asm "vmov.f32 $0, $1", "=w,w"(bfloat %x)
+  ret bfloat %0
+}