[PATCH] D135844: [AArch64]Regard (shl val, N) as a potential bit-field-positioning op regardless of the number of uses; the rationale is that, 'val' could be used as bit extraction source as long as N (the left shift amount) fits BiggerPattern requirement
Mingming Liu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 12 19:52:31 PDT 2022
mingmingl created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
mingmingl requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D135844
Files:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/test/CodeGen/AArch64/bitfield-insert.ll
Index: llvm/test/CodeGen/AArch64/bitfield-insert.ll
===================================================================
--- llvm/test/CodeGen/AArch64/bitfield-insert.ll
+++ llvm/test/CodeGen/AArch64/bitfield-insert.ll
@@ -266,10 +266,9 @@
; CHECK-LABEL: test_nouseful_bits:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: bfi w0, w8, #8, #8
; CHECK-NEXT: lsl w8, w8, #8
-; CHECK-NEXT: mov w9, w8
-; CHECK-NEXT: bfxil w9, w0, #0, #8
-; CHECK-NEXT: bfi w8, w9, #16, #16
+; CHECK-NEXT: bfi w8, w0, #16, #16
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: ret
%conv = zext i8 %a to i32 ; 0 0 0 A
Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2556,9 +2556,6 @@
if (!isOpcWithIntImmediate(N, ISD::SHL, ShlImm))
return false;
- if (!BiggerPattern && !Op.hasOneUse())
- return false;
-
EVT VT = N->getValueType(0);
assert((VT == MVT::i32 || VT == MVT::i64) &&
"Caller guarantees that type is i32 or i64");
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