[llvm] 575eed3 - AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-10-12T17:25:24-07:00
New Revision: 575eed3dace3c9c741cfc47be02ea1dee4b0402b

URL: https://github.com/llvm/llvm-project/commit/575eed3dace3c9c741cfc47be02ea1dee4b0402b
DIFF: https://github.com/llvm/llvm-project/commit/575eed3dace3c9c741cfc47be02ea1dee4b0402b.diff

LOG: AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs

If inline asm has a VGPR def, it must have come from a VGPR write
somewhere inside the asm. This should be further extended to all
read after write hazards.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    llvm/test/CodeGen/AMDGPU/mai-hazards.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 9f504f6d21563..fb300e81cca8a 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1961,7 +1961,7 @@ int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) {
   unsigned Opc = MI->getOpcode();
 
   auto IsVALUFn = [](const MachineInstr &MI) {
-    return SIInstrInfo::isVALU(MI);
+    return SIInstrInfo::isVALU(MI) || MI.isInlineAsm();
   };
 
   if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write

diff  --git a/llvm/test/CodeGen/AMDGPU/mai-hazards.mir b/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
index 370ef4f63577c..dcbf2b8e3842d 100644
--- a/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
+++ b/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
@@ -24,6 +24,64 @@ body:             |
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
 ...
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_partialnop
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_partialnop
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    S_NOP 0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_otherreg
+# GCN:      INLINEASM
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_otherreg
+body:             |
+  bb.0:
+    liveins: $vgpr0
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr1
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: bundle_write_vgpr_accvgpr_write_read
+# GCN: BUNDLE
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_MOV_B32
+# GCN-NEXT: }
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            bundle_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+    $vgpr0 = BUNDLE {
+      S_NOP 0
+      $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+    }
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr