[PATCH] D135794: [RISCV] Use vslide1up for inserting bottom element into splat vector

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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This patch adds a DAG combine to replace a vmv.s.x into a splat vector with a vslide1up instead.  This relies on the fact that we can shift a splat without changing any of the active lanes, and vslide1up has separate source and destination vector registers.  This allows vslide1up to be tail agnostic whereas vmv.s.x has to be tail undisturbed.  This in turn avoids the need for a vsetvli toggle.

One downside to this conversation is that vslide1up has a restriction that the source and destination vector registers can't overlap.  This increases register pressure locally, and particularly at very high LMUL, could force an additional spill for a value live over the vslide1up.  I think this is net worthwhile, but I'm curious what others think.

There are several TODOs noted in the patch.  I plan on implementing the vmv.s.f and narrower element types in a follow up patch.  I don't plan to bother with the wider VL one.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135794

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/fold-vector-cmp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

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