[PATCH] D135782: [AMDGPU] Add GFX11 tests for fcmp and ballot. NFC
Joe Nash via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 12 07:55:12 PDT 2022
Joe_Nash created this revision.
Joe_Nash added reviewers: arsenm, foad, Leonc.
Herald added subscribers: kosarev, kerbowa, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
Joe_Nash requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D135782
Files:
llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
Index: llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
+++ llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK %s
-define amdgpu_kernel void @test() {
-; CHECK-LABEL: test:
+define amdgpu_kernel void @icmp_test() {
+; CHECK-LABEL: icmp_test:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: v_cmp_eq_u16_e64 s0, 0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, 0
@@ -15,12 +15,55 @@
entry:
%0 = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32)
%cmp0 = icmp eq i64 %0, 0
- %add0 = zext i1 %cmp0 to i32
- store i32 %add0, ptr addrspace(3) null, align 2147483648
+ %zext0 = zext i1 %cmp0 to i32
+ store i32 %zext0, ptr addrspace(3) null, align 2147483648
+ ret void
+}
+
+define amdgpu_kernel void @fcmp_test(half %x, half %y) {
+; CHECK-LABEL: fcmp_test:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_load_b32 s0, s[0:1], 0x0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_lshr_b32 s1, s0, 16
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_cmp_le_f16_e64 s0, s0, s1
+; CHECK-NEXT: s_cmp_eq_u32 s0, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: ds_store_b32 v1, v0
+; CHECK-NEXT: s_endpgm
+entry:
+ %0 = tail call i64 @llvm.amdgcn.fcmp.i64.f16(half %x, half %y, i32 5)
+ %cmp0 = icmp eq i64 %0, 0
+ %zext0 = zext i1 %cmp0 to i32
+ store i32 %zext0, ptr addrspace(3) null, align 2147483648
+ ret void
+}
+
+define amdgpu_kernel void @ballot_test(half %x, half %y) {
+; CHECK-LABEL: ballot_test:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_b32 s0, s[0:1], 0x0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_lshr_b32 s1, s0, 16
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_cmp_eq_f16_e64 s0, s0, s1
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; CHECK-NEXT: ds_store_b32 v0, v1
+; CHECK-NEXT: s_endpgm
+ %cmp = fcmp oeq half %x, %y
+ %ballot = tail call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
+ store i32 %ballot, ptr addrspace(3) null, align 2147483648
ret void
}
-; Function Attrs: convergent nounwind readnone willreturn
declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #0
+declare i64 @llvm.amdgcn.fcmp.i64.f16(half, half, i32 immarg) #0
+
+declare i32 @llvm.amdgcn.ballot.i32(i1) #0
+
attributes #0 = { convergent nounwind readnone willreturn }
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D135782.467151.patch
Type: text/x-patch
Size: 2849 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221012/b4b2a1e2/attachment.bin>
More information about the llvm-commits
mailing list