[PATCH] D135455: [AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 12 07:34:42 PDT 2022


sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1043
 
+def ZZ_s_r  : RegisterOperand<ZPR2, "printTypedVectorList<0,'s',2,true>"> {
+  let ParserMatchClass = ZPRVectorList<32, 2>;
----------------
nit: Can you add `/*Stride=*/2, /*PrintRange=*/true` to make it clear what these operands mean?


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1415
 
+// SME2 register operands and classes
+def MatrixOp32 : MatrixOperand<MPR, 32>;
----------------
Can you move these definitions to line 1368 (after `def MatrixOp : ...` ?)


================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:250
+let Predicates = [HasSME2] in {
+
+defm ADD_VG2_M2ZZ_S  : sme2_mul_add_sub_array_vg2_single_S<"add", 0b10>;
----------------
nit: please remove newline


================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:262
+defm FMLS_VG4_M4ZZ_S  : sme2_mul_add_sub_array_vg4_single_S<"fmls", 0b01>;
+
+}
----------------
nit: please remove newline


================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:267
+let Predicates = [HasSME2, HasSMEI64] in {
+
+defm ADD_VG2_M2ZZ_D  : sme2_mul_add_sub_array_vg2_single_D<"add", 0b10>;
----------------
nit: please remove newline


================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:276
+let Predicates = [HasSME2, HasSMEF64] in {
+defm FMLA_VG2_M2ZZ_D  : sme2_mul_add_sub_array_vg2_single_D<"fmla", 0b00>;
+defm FMLA_VG4_M4ZZ_D  : sme2_mul_add_sub_array_vg4_single_D<"fmla", 0b00>;
----------------
Did you mean `mla_add_sub` ?


================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:281
+defm FMLS_VG4_M4ZZ_D  : sme2_mul_add_sub_array_vg4_single_D<"fmls", 0b01>;
+
+}
----------------
nit: please remove newline


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3143
+    if (DotPosition != StringRef::npos) {
+      const auto &KindRes =
+          parseVectorKind(Name.drop_front(DotPosition), RegKind::Matrix);
----------------
drop const?


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4239
+
+  if (!VG.size())
+    return true;
----------------
nit: `s/!VG.size()/VG.empty()/`


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1195
+//===----------------------------------------------------------------------===//
+// SME2 single-multi ternary int/fp  two/four registers
+
----------------
nit: `s/  /, /`


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  https://reviews.llvm.org/D135455/new/

https://reviews.llvm.org/D135455



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