[llvm] 2639caf - [InstCombine] add "exact" to div tests to show missing propagation; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 12 06:26:43 PDT 2022
Author: Sanjay Patel
Date: 2022-10-12T09:25:04-04:00
New Revision: 2639caf5608af0b0273a193e0f45f8f965daa21e
URL: https://github.com/llvm/llvm-project/commit/2639caf5608af0b0273a193e0f45f8f965daa21e
DIFF: https://github.com/llvm/llvm-project/commit/2639caf5608af0b0273a193e0f45f8f965daa21e.diff
LOG: [InstCombine] add "exact" to div tests to show missing propagation; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/div-shift.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/div-shift.ll b/llvm/test/Transforms/InstCombine/div-shift.ll
index 0100886a0350..d357ec742894 100644
--- a/llvm/test/Transforms/InstCombine/div-shift.ll
+++ b/llvm/test/Transforms/InstCombine/div-shift.ll
@@ -311,15 +311,15 @@ define i5 @sdiv_mul_shl_nsw(i5 %x, i5 %y, i5 %z) {
; (Y * Z) s/ (X << Z) --> Y s/ (1 << Z)
-define i5 @sdiv_mul_shl_nsw_commute1(i5 %x, i5 %y, i5 %z) {
-; CHECK-LABEL: @sdiv_mul_shl_nsw_commute1(
+define i5 @sdiv_mul_shl_nsw_exact_commute1(i5 %x, i5 %y, i5 %z) {
+; CHECK-LABEL: @sdiv_mul_shl_nsw_exact_commute1(
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i5 1, [[Z:%.*]]
; CHECK-NEXT: [[D:%.*]] = sdiv i5 [[Y:%.*]], [[TMP1]]
; CHECK-NEXT: ret i5 [[D]]
;
%m1 = mul nsw i5 %y, %x
%m2 = shl nsw i5 %x, %z
- %d = sdiv i5 %m1, %m2
+ %d = sdiv exact i5 %m1, %m2
ret i5 %d
}
@@ -451,14 +451,14 @@ define i5 @udiv_mul_shl_nuw(i5 %x, i5 %y, i5 %z) {
; (Y * X) u/ (X << Z) --> Y u>> Z
-define i5 @udiv_mul_shl_nuw_commute1(i5 %x, i5 %y, i5 %z) {
-; CHECK-LABEL: @udiv_mul_shl_nuw_commute1(
+define i5 @udiv_mul_shl_nuw_exact_commute1(i5 %x, i5 %y, i5 %z) {
+; CHECK-LABEL: @udiv_mul_shl_nuw_exact_commute1(
; CHECK-NEXT: [[D:%.*]] = lshr i5 [[Y:%.*]], [[Z:%.*]]
; CHECK-NEXT: ret i5 [[D]]
;
%m1 = mul nuw i5 %y, %x
%m2 = shl nuw i5 %x, %z
- %d = udiv i5 %m1, %m2
+ %d = udiv exact i5 %m1, %m2
ret i5 %d
}
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