[PATCH] D135441: [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.

In D135441#3852104 <https://reviews.llvm.org/D135441#3852104>, @dmgreen wrote:

> Out of interest, what cases do you have where mul is worse than add+shift + add+shift? From the look of the tv100 scheduling model it would seem to be 3/4 cycles for the mul (depending on whether it is i32 or i64) vs 2+2 for the add+shifts. Are small shifts really free, as in FeatureLSLFast?

I read from the a new spec , which I'm working on, the Latency of  add+shifts is 1 when the value of shift small.  At the same time, I happen to see a **TODO **in the upstream code :)
Thanks for your detail suggestion, I'll add the check of FeatureLSLFast or distinguish more shift-related values.


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