[PATCH] D135324: [AArch64-SVE]: force using SVE in streaming mode to lower arithmetic and logical fixed-width vector ops.

Hassnaa Hamdi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 11 22:13:22 PDT 2022


hassnaa-arm updated this revision to Diff 467017.
hassnaa-arm added a comment.

Fix invalid bic instruction in streaming mode.
Fix invalid bic instruction that was generated during 'and' combining by converting the fixed-length vector to scalable one to combine SVEAnd instead of and.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135324/new/

https://reviews.llvm.org/D135324

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll

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