[PATCH] D135693: [WIP][RegisterScavenger][RISCV] Don't search for FrameSetup instrs if we were searching from Non-FrameSetup instrs
luxufan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 11 20:08:30 PDT 2022
StephenFan added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir:27
; CHECK-NEXT: addi s0, sp, 2032
+ ; CHECK-NEXT: sd a0, 0(sp)
+ ; CHECK-NEXT: lui a0, 2
+ ; CHECK-NEXT: addiw a0, a0, -2032
+ ; CHECK-NEXT: sub sp, sp, a0
+ ; CHECK-NEXT: srli a0, sp, 12
+ ; CHECK-NEXT: slli sp, a0, 12
+ ; CHECK-NEXT: ld a0, 0(sp)
; CHECK-NEXT: sd a1, 0(sp)
- ; CHECK-NEXT: lui a1, 2
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The code here seems incorrect. Here `a1` is stored to 0(sp) before `sub sp, sp, a1` but restored after `sub sp, sp, a1`.
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Comment at: llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir:20
; CHECK-NEXT: addi sp, sp, -272
; CHECK-NEXT: sd a0, 8(sp)
; CHECK-NEXT: csrr a0, vlenb
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See the comment above.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D135693/new/
https://reviews.llvm.org/D135693
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