[PATCH] D135396: [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1bdf21d55ca7: [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135396/new/

https://reviews.llvm.org/D135396

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll