[PATCH] D135704: AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: AMDGPU, rampitec, kerbowa.
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If inline asm has a VGPR def, it must have come from a VGPR write
somewhere inside the asm. This should be further extended to all
read after write hazards.


https://reviews.llvm.org/D135704

Files:
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/test/CodeGen/AMDGPU/mai-hazards.mir


Index: llvm/test/CodeGen/AMDGPU/mai-hazards.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/mai-hazards.mir
+++ llvm/test/CodeGen/AMDGPU/mai-hazards.mir
@@ -24,6 +24,64 @@
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
 ...
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_partialnop
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_partialnop
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    S_NOP 0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_otherreg
+# GCN:      INLINEASM
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_otherreg
+body:             |
+  bb.0:
+    liveins: $vgpr0
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr1
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: bundle_write_vgpr_accvgpr_write_read
+# GCN: BUNDLE
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_MOV_B32
+# GCN-NEXT: }
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            bundle_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+    $vgpr0 = BUNDLE {
+      S_NOP 0
+      $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+    }
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1961,7 +1961,7 @@
   unsigned Opc = MI->getOpcode();
 
   auto IsVALUFn = [](const MachineInstr &MI) {
-    return SIInstrInfo::isVALU(MI);
+    return SIInstrInfo::isVALU(MI) || MI.isInlineAsm();
   };
 
   if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write


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