[PATCH] D135146: [GISel] Add redundant bitcast folding combine

[Pierre van Houtryve via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4d815bfae0ea: [GISel] Add redundant bitcast folding combine (authored by Pierre-vh).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135146/new/

https://reviews.llvm.org/D135146

Files:
  llvm/include/llvm/Target/GlobalISel/Combine.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir


Index: llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: s32_bitcast
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: s32_bitcast
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %b1:_(s32) = G_BITCAST %src
+    %b2:_(<2 x s16>) = G_BITCAST %b1
+    $vgpr0 = COPY %b2
+...
+
+---
+name: s64_bitcast
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: s64_bitcast
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %src(<2 x s32>)
+    %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %b1:_(s64) = G_BITCAST %src
+    %b2:_(<2 x s32>) = G_BITCAST %b1
+    $vgpr0_vgpr1 = COPY %b2
+...
+
+---
+name: s64_bitcast_differentypes_nofold
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: s64_bitcast_differentypes_nofold
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: %b1:_(s64) = G_BITCAST %src(<2 x s32>)
+    ; CHECK-NEXT: %b2:_(<4 x s16>) = G_BITCAST %b1(s64)
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %b2(<4 x s16>)
+    %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %b1:_(s64) = G_BITCAST %src
+    %b2:_(<4 x s16>) = G_BITCAST %b1
+    $vgpr0_vgpr1 = COPY %b2
+...
Index: llvm/include/llvm/Target/GlobalISel/Combine.td
===================================================================
--- llvm/include/llvm/Target/GlobalISel/Combine.td
+++ llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -967,6 +967,12 @@
          [{ return Helper.matchSubAddSameReg(*${root}, ${matchinfo}); }]),
   (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
 
+def bitcast_bitcast_fold : GICombineRule<
+  (defs root:$dst),
+  (match (G_BITCAST $dst, $src1):$op, (G_BITCAST $src1, $src0),
+      [{ return MRI.getType(${src0}.getReg()) == MRI.getType(${dst}.getReg()); }]),
+  (apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${src0}.getReg()); }])>;
+
 def select_to_minmax: GICombineRule<
   (defs root:$root, build_fn_matchinfo:$info),
   (match (wip_match_opcode G_SELECT):$root,
@@ -993,7 +999,8 @@
                                         fneg_fneg_fold, right_identity_one,
                                         add_sub_reg, buildvector_identity_fold,
                                         trunc_buildvector_fold,
-                                        trunc_lshr_buildvector_fold]>;
+                                        trunc_lshr_buildvector_fold,
+                                        bitcast_bitcast_fold]>;
 
 def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p,
                                      overlapping_and, mulo_by_2, mulo_by_0,


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