[llvm] ac4f3ff - [SDAG] Clarify behavior of scalable demanded/undef elts in isSplatValue [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-10-11T07:28:34-07:00
New Revision: ac4f3fff8c85f30782391d4500938ca1ec62d3d9

URL: https://github.com/llvm/llvm-project/commit/ac4f3fff8c85f30782391d4500938ca1ec62d3d9
DIFF: https://github.com/llvm/llvm-project/commit/ac4f3fff8c85f30782391d4500938ca1ec62d3d9.diff

LOG: [SDAG] Clarify behavior of scalable demanded/undef elts in isSplatValue [nfc]

Update comment, and add an assertion to check property expected by sole (non-test) caller.  Remove tests which appear to have been copied from fixed vector tests, and whose demanded bits don't correspond to the way this interface is otherwise used.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f93794f05de0e..219d58af6b44c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2543,13 +2543,16 @@ bool SelectionDAG::MaskedValueIsAllOnes(SDValue V, const APInt &Mask,
 
 /// isSplatValue - Return true if the vector V has the same value
 /// across all DemandedElts. For scalable vectors it does not make
-/// sense to specify which elements are demanded or undefined, therefore
-/// they are simply ignored.
+/// sense to specify which elements are demanded, therefore they are
+/// simply ignored.  For undef elts this means either all lanes are
+/// undef, or no lanes are known undef.
 bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
                                 APInt &UndefElts, unsigned Depth) const {
   unsigned Opcode = V.getOpcode();
   EVT VT = V.getValueType();
   assert(VT.isVector() && "Vector type expected");
+  assert((!VT.isScalableVector() || DemandedElts.getBitWidth() == 1) &&
+         "scalable demanded bits are ignored");
 
   if (!VT.isScalableVector() && !DemandedElts)
     return false; // No demanded elts, better to assume we don't know anything.

diff  --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
index 94171001691fc..428309b262a7e 100644
--- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
@@ -327,10 +327,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
   APInt UndefElts;
   APInt DemandedElts;
   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
-
-  // Width=16, Mask=3. These bits should be ignored.
-  DemandedElts = APInt(16, 3);
-  EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
 }
 
 TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
@@ -351,10 +347,6 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
   APInt UndefElts;
   APInt DemandedElts;
   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
-
-  // Width=16, Mask=3. These bits should be ignored.
-  DemandedElts = APInt(16, 3);
-  EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
 }
 
 TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {