[PATCH] D135619: [RISCV][LegalizeTypes][TargetLowering] Add a target hook to limit alignment of scalable vectors in SelectionDAG::getReducedAlign.

[Craig Topper via Phabricator via llvm-commits]

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getReducedAlign is used by LegalizeTypes to when creating stack
temporaries for some vector operations that can't be easily split
into vectors with fewer elements. For example, insert and extract
elements/subvectors.

Scalable vector stack temporaries do not update the maximum stack
alignment in MachineFunctionInfo. If a scalable vector temporary is
created with alignment larger than the maximum stack alignment and
larger than the 16 byte guaranteed for RISC-V, we will fail to
reserve the frame pointer prior to register allocation. But prologue
epilogue emitter will try to use it to align the stack for the vectors.
Since it wasn't reserved for register allocation, it might be used
for something else before the epilogue.

I've also limited some stack temporaries created by argument lowering
and have added a check to ensure the FP was reserved for regalloc. I'll
probably split that into separate patch, but wanted everything together
for initial discussion.

Fixes PR57939.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135619

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll

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