[PATCH] D135441: [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

`MF.getSubtarget().getSchedModel()` should work in SelectionDAG.

The tricky things here are:

- Actually getting the right variant out of the scheduler is a little tricky.  You basically have to construct an MCInst.  (Note that the latency can vary depending on the shirt amount.)
- We don't have actually have accurate scheduling models for all the chips we care about.  It tends to be something that requires a lot of effort for very little effect, so a lot of CPUs just use the A57 model.

Maybe to start, just try to figure out which targets have "free" shifts, and turn on the optimization for the cases that involve those shifts?  (Multiple cores have a small shift optimization, where left shifts of 4 or less don't increase the latency of an add.)


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https://reviews.llvm.org/D135441