[PATCH] D135593: [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
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This patch implements:
 FCVTZS: Multi-vector floating-point convert to signed integer, rounding

  toward zero.

FCVTZU: Multi-vector floating-point convert to unsigned integer,

  rounding toward zero.

SCVTF: Multi-vector signed integer convert to floating-point.
 UCVTF: Multi-vector unsigned integer convert to floating-point.
for 2 and 4 registers

The reference can be found here:

  https://developer.arm.com/documentation/ddi0602/2022-09
  
  Depends on: D135563


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135593

Files:
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s
  llvm/test/MC/AArch64/SME2/fcvtzs.s
  llvm/test/MC/AArch64/SME2/fcvtzu-diagnostics.s
  llvm/test/MC/AArch64/SME2/fcvtzu.s
  llvm/test/MC/AArch64/SME2/scvtf-diagnostics.s
  llvm/test/MC/AArch64/SME2/scvtf.s
  llvm/test/MC/AArch64/SME2/ucvtf-diagnostics.s
  llvm/test/MC/AArch64/SME2/ucvtf.s

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