[llvm] ebb258d - [AMDGPU] Make V_SAT_PK_U8_I16 a True16 Instruction

[Joe Nash via llvm-commits]

Author: Joe Nash
Date: 2022-10-10T10:33:49-04:00
New Revision: ebb258d3b0785f6dcc65e1f277d0690891ddc94d

URL: https://github.com/llvm/llvm-project/commit/ebb258d3b0785f6dcc65e1f277d0690891ddc94d
DIFF: https://github.com/llvm/llvm-project/commit/ebb258d3b0785f6dcc65e1f277d0690891ddc94d.diff

LOG: [AMDGPU] Make V_SAT_PK_U8_I16 a True16 Instruction

The return type is two u8 packed into a 16 bit VGPR, so this instruction
should be True16.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D135478

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.td
    llvm/lib/Target/AMDGPU/VOP1Instructions.td
    llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
    llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 6a0ac73a962db..89ce127933f68 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2659,6 +2659,7 @@ def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
 
 def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
 def VOP_I32_I16 : VOPProfile <[i32, i16, untyped, untyped]>;
+def VOP_I16_I32 : VOPProfile <[i16, i32, untyped, untyped]>;
 
 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;

diff  --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 06c863dedd12f..85db94bff7640 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -548,7 +548,7 @@ let SubtargetPredicate = isGFX9Plus in {
   }
 
   let isReMaterializable = 1 in
-  defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
+  defm V_SAT_PK_U8_I16    : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>;
 
   let mayRaiseFPException = 0 in {
     let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
@@ -822,6 +822,7 @@ defm V_RNDNE_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05e, "v_rndne_f16">;
 defm V_FRACT_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05f, "v_fract_f16">;
 defm V_SIN_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x060, "v_sin_f16">;
 defm V_COS_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x061, "v_cos_f16">;
+defm V_SAT_PK_U8_I16_t16     : VOP1_Real_FULL_t16_gfx11<0x062, "v_sat_pk_u8_i16">;
 defm V_CVT_NORM_I16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x063, "v_cvt_norm_i16_f16">;
 defm V_CVT_NORM_U16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x064, "v_cvt_norm_u16_f16">;
 
@@ -904,7 +905,7 @@ defm V_RNDNE_F16         : VOP1_Real_gfx10<0x05e>;
 defm V_FRACT_F16         : VOP1_Real_gfx10<0x05f>;
 defm V_SIN_F16           : VOP1_Real_gfx10<0x060>;
 defm V_COS_F16           : VOP1_Real_gfx10<0x061>;
-defm V_SAT_PK_U8_I16     : VOP1_Real_gfx10_FULL_gfx11<0x062>;
+defm V_SAT_PK_U8_I16     : VOP1_Real_gfx10<0x062>;
 defm V_CVT_NORM_I16_F16  : VOP1_Real_gfx10<0x063>;
 defm V_CVT_NORM_U16_F16  : VOP1_Real_gfx10<0x064>;
 

diff  --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index b62520d656d88..6f9ae7b5c6a8d 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -181,6 +181,9 @@ v_rsq_f16_e32 v255, v1
 v_rsq_f16_e32 v5, v199
 // GFX11: error: operands are not valid for this GPU or mode
 
+v_sat_pk_u8_i16_e32 v199, v5
+// GFX11: error: operands are not valid for this GPU or mode
+
 v_sin_f16_e32 v128, 0xfe0b
 // GFX11: error: operands are not valid for this GPU or mode
 
@@ -334,6 +337,9 @@ v_rsq_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 v_rsq_f16_e32 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
+v_sat_pk_u8_i16_e32 v199, v5 quad_perm:[3,2,1,0]
+// GFX11: error: invalid operand for instruction
+
 v_sin_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
@@ -478,6 +484,9 @@ v_rsq_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 v_rsq_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
+v_sat_pk_u8_i16_e32 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: error: invalid operand for instruction
+
 v_sin_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 

diff  --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
index 0fefb9b6a8d72..ed8b1d5b7237b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
@@ -919,6 +919,9 @@ v_rsq_f16 v255, vcc_lo
 v_rsq_f16 v5, v199
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v128, 0xfe0b
 // GFX11: v_sin_f16_e64
 
@@ -1240,6 +1243,9 @@ v_rsq_f16 v255, v127 quad_perm:[3,2,1,0]
 v_rsq_f16 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5 quad_perm:[3,2,1,0]
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: v_sin_f16_e64
 
@@ -1444,6 +1450,9 @@ v_rsq_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
 v_rsq_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_sin_f16_e64