[PATCH] D134477: [X86] Lower vector interleave into unpck and perm

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:17786
+                                                 SelectionDAG &DAG) {
+  if (VT != MVT::v32i8 || Mask.size() != 32)
+    return SDValue();
----------------
Have you investigated using this for other types?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:17819
+  ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(Shuffles[0]);
+  ShuffleVectorSDNode *SVN2 = cast<ShuffleVectorSDNode>(Shuffles[1]);
+  SDNode *FirstHalf;
----------------
auto *SVN1
auto *SVN2


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134477/new/

https://reviews.llvm.org/D134477