[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation
Zixuan Wu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 10 02:22:02 PDT 2022
zixuan-wu added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:106
+ for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
+ markSuperRegs(Reserved, Reg);
+
----------------
I am wondering whether we need construct another new RegisterClass for RV32E instead of GPR, for example eGPR, so that the num and other info such as weight, etc of RegisterClass can adjust. Then the reserved logic is not necessary.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D70401/new/
https://reviews.llvm.org/D70401
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