[PATCH] D135560: [ARM] Add errors for MVE exclusive registers.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
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These instructions already had errors for operands that could not share the same register

- VCMUL, VMULL, VQDMULL.

This extends that to a few others:

- VREV64, VQDMULLqr, VCADD and VHCADD.

Only the i32 types require the error.


https://reviews.llvm.org/D135560

Files:
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/test/MC/ARM/mve-qdest-qsrc.s


Index: llvm/test/MC/ARM/mve-qdest-qsrc.s
===================================================================
--- llvm/test/MC/ARM/mve-qdest-qsrc.s
+++ llvm/test/MC/ARM/mve-qdest-qsrc.s
@@ -466,11 +466,47 @@
 
 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
 vqdmullb.s32 q0, q1, q0
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqdmullb.s32 q0, q0, q1
 
 vqdmullt.s16 q0, q1, q2
 # CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
 # CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
 
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqdmullb.s32 q0, q0, r0
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqdmullt.s32 q0, q0, r0
+
+vqdmullb.s16 q0, q0, r0
+# CHECK: vqdmullb.s16 q0, q0, r0 @ encoding: [0x30,0xee,0x60,0x0f]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vcadd.s32 q0, q1, q0, #270
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vcadd.f32 q0, q1, q0, #270
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vhcadd.s32 q0, q1, q0, #270
+
+vcadd.s32 q0, q0, q1, #270
+# CHECK: vcadd.i32 q0, q0, q1, #270 @ encoding: [0x20,0xfe,0x02,0x1f]
+vcadd.f32 q0, q0, q1, #270
+# CHECK: vcadd.f32 q0, q0, q1, #270 @ encoding: [0x90,0xfd,0x42,0x08]
+vhcadd.s32 q0, q0, q1, #270
+# CHECK: vhcadd.s32 q0, q0, q1, #270 @ encoding: [0x20,0xee,0x02,0x1f]
+vhcadd.s16 q0, q0, q1, #270
+# CHECK: vhcadd.s16 q0, q0, q1, #270 @ encoding: [0x10,0xee,0x02,0x1f]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vrev64.8 q0, q0
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vrev64.16 q0, q0
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vrev64.32 q0, q0
+
+vrev32.8 q0, q0
+# CHECK: vrev32.8 q0, q0 @ encoding: [0xb0,0xff,0xc0,0x00]
+
 vpste
 vqdmulltt.s32 q0, q1, q2
 vqdmullbe.s16 q0, q1, q2
Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8279,6 +8279,26 @@
     }
     break;
   }
+  case ARM::MVE_VREV64_8:
+  case ARM::MVE_VREV64_16:
+  case ARM::MVE_VREV64_32:
+  case ARM::MVE_VQDMULL_qr_s32bh:
+  case ARM::MVE_VQDMULL_qr_s32th: {
+    if (Operands[3]->getReg() == Operands[4]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qn register can't be identical");
+    }
+    break;
+  }
+  case ARM::MVE_VCADDi32:
+  case ARM::MVE_VCADDf32:
+  case ARM::MVE_VHCADDs32: {
+    if (Operands[3]->getReg() == Operands[5]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qm register can't be identical");
+    }
+    break;
+  }
   case ARM::MVE_VMOV_rr_q: {
     if (Operands[4]->getReg() != Operands[6]->getReg())
       return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");


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