[llvm] a835b92 - [RISCV] Use hasAllWUsers to recover XORI/ORI
via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 9 23:16:59 PDT 2022
Author: LiaoChunyu
Date: 2022-10-10T14:16:50+08:00
New Revision: a835b92e6c309460d0c225545d312eb15556a90a
URL: https://github.com/llvm/llvm-project/commit/a835b92e6c309460d0c225545d312eb15556a90a
DIFF: https://github.com/llvm/llvm-project/commit/a835b92e6c309460d0c225545d312eb15556a90a.diff
LOG: [RISCV] Use hasAllWUsers to recover XORI/ORI
reference 0fbe71e91f44.
Also add testcase for addi.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D135538
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index a3ad883ed42ca..1ff1ea138e06a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2245,6 +2245,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB ||
Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::AND ||
+ Node->getOpcode() == ISD::OR || Node->getOpcode() == ISD::XOR ||
Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
isa<ConstantSDNode>(Node)) &&
"Unexpected opcode");
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 640e795b0ee3f..4c8d54cc2c4ed 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1688,10 +1688,14 @@ def : Pat<(binop_allwusers<srl> (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
// Use binop_allwusers to recover immediates that may have been broken by
// SimplifyDemandedBits.
-// TODO: This is valid for ADDI/ORI/XORI.
def : Pat<(binop_allwusers<and> GPR:$rs1, u32simm12:$imm),
(ANDI GPR:$rs1, u32simm12:$imm)>;
+def : Pat<(binop_allwusers<or> GPR:$rs1, u32simm12:$imm),
+ (ORI GPR:$rs1, u32simm12:$imm)>;
+
+def : Pat<(binop_allwusers<xor> GPR:$rs1, u32simm12:$imm),
+ (XORI GPR:$rs1, u32simm12:$imm)>;
/// Loads
defm : LdPat<sextloadi32, LW, i64>;
diff --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index 24b5bc3221b65..295be3f52b82c 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -118,6 +118,45 @@ define signext i32 @andi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
ret i32 %5
}
+define signext i32 @addi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: addi_sub_cse:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: addiw a0, a0, -8
+; CHECK-NEXT: sw a0, 0(a2)
+; CHECK-NEXT: ret
+ %4 = add i32 %0, -8
+ %5 = sub i32 %4, %1
+ store i32 %5, ptr %2, align 4
+ ret i32 %5
+}
+
+define signext i32 @xori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: xori_sub_cse:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xori a0, a0, -8
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: sw a0, 0(a2)
+; CHECK-NEXT: ret
+ %4 = xor i32 %0, -8
+ %5 = sub i32 %4, %1
+ store i32 %5, ptr %2, align 4
+ ret i32 %5
+}
+
+define signext i32 @ori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: ori_sub_cse:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, -8
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: sw a0, 0(a2)
+; CHECK-NEXT: ret
+ %4 = or i32 %0, -8
+ %5 = sub i32 %4, %1
+ store i32 %5, ptr %2, align 4
+ ret i32 %5
+}
+
; SimplifyDemandedBits breaks the ANDI by turning -8 into 0xfffffff8. This
; gets CSEd with the AND needed for type legalizing the lshr. This increases
; the use count of the AND with 0xfffffff8 making TargetShrinkDemandedConstant
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