[llvm] bc5e969 - [PowerPC] Add vector pair calling convention for AIX
Ting Wang via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 8 22:24:26 PDT 2022
Author: Ting Wang
Date: 2022-10-09T01:23:18-04:00
New Revision: bc5e969ca1e1567ae5ad259f7f2d55a96e30b07f
URL: https://github.com/llvm/llvm-project/commit/bc5e969ca1e1567ae5ad259f7f2d55a96e30b07f
DIFF: https://github.com/llvm/llvm-project/commit/bc5e969ca1e1567ae5ad259f7f2d55a96e30b07f.diff
LOG: [PowerPC] Add vector pair calling convention for AIX
This is AIX part of update after https://reviews.llvm.org/D117225
Fixed the issue that AIX64 with vector pair enabled saw redundant
spill/reload of callee saved vector registers.
Based on original patch by: Kai Luo
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D133466
Added:
Modified:
llvm/lib/Target/PowerPC/PPCCallingConv.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
index 8f9dc98c32132..9df1b1dbd5981 100644
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -386,3 +386,9 @@ def CSR_SVR64_ColdCC_R2_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC_VSRP, X2)>;
def CSR_64_AllRegs_VSRP :
CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
+
+def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
+
+def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
+
+def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index a60b993ca7280..d39934bd32c1a 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -237,8 +237,14 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
// Standard calling convention CSRs.
if (TM.isPPC64()) {
- if (Subtarget.pairedVectorMemops())
+ if (Subtarget.pairedVectorMemops()) {
+ if (Subtarget.isAIXABI()) {
+ if (!TM.getAIXExtendedAltivecABI())
+ return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
+ return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
+ }
return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
+ }
if (Subtarget.hasAltivec() &&
(!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
@@ -248,6 +254,9 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
// 32-bit targets.
if (Subtarget.isAIXABI()) {
+ if (Subtarget.pairedVectorMemops())
+ return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
+ : CSR_AIX32_SaveList;
if (Subtarget.hasAltivec())
return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
: CSR_AIX32_SaveList;
@@ -286,6 +295,11 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
}
if (Subtarget.isAIXABI()) {
+ if (Subtarget.pairedVectorMemops()) {
+ if (!TM.getAIXExtendedAltivecABI())
+ return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+ return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
+ }
return TM.isPPC64()
? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
? CSR_PPC64_Altivec_RegMask
diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
index c532a432a0712..34db2e36dac66 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
@@ -3,32 +3,20 @@
; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
; CHECK-LABEL: name: foo
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
; CHECK-VEXT-LABEL: name: foo
; CHECK-VEXT-NOT: spill-slot
@@ -50,32 +38,20 @@ entry:
ret void
}
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
; CHECK-LABEL: name: spill
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
; CHECK-VEXT-LABEL: name: spill
; CHECK-VEXT: spill-slot
diff --git a/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
index fb4e5ae0761b6..1c89a5ba6121b 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
@@ -9,19 +9,7 @@ define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
-; CHECK-NEXT: stdu 1, -320(1)
-; CHECK-NEXT: stxv 52, 128(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 53, 144(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 54, 160(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 55, 176(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 56, 192(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 57, 208(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 58, 224(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 59, 240(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 60, 256(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 61, 272(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 62, 288(1) # 16-byte Folded Spill
-; CHECK-NEXT: stxv 63, 304(1) # 16-byte Folded Spill
+; CHECK-NEXT: stdu 1, -128(1)
; CHECK-NEXT: std 3, 120(1)
; CHECK-NEXT: ld 3, 120(1)
; CHECK-NEXT: ld 4, 0(3)
@@ -37,19 +25,7 @@ define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 {
; CHECK-NEXT: ld 2, 40(1)
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-NEXT: extsw 3, 3
-; CHECK-NEXT: lxv 63, 304(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 62, 288(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 61, 272(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 60, 256(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 59, 240(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 58, 224(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 57, 208(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 56, 192(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 55, 176(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 54, 160(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 53, 144(1) # 16-byte Folded Reload
-; CHECK-NEXT: lxv 52, 128(1) # 16-byte Folded Reload
-; CHECK-NEXT: addi 1, 1, 320
+; CHECK-NEXT: addi 1, 1, 128
; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
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