[PATCH] D135527: [LoongArch] Define getSetCCResultType for setting vector setCC type
wanglei via Phabricator via llvm-commits
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Sat Oct 8 20:23:52 PDT 2022
wangleiat created this revision.
wangleiat added reviewers: SixWeining, xen0n, xry111, gonglingqin, MaskRay.
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To avoid trigger "No default SetCC type for vectors!" Assertion.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D135527
Files:
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.h
llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
Index: llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+define void @getSetCCResultType(ptr %p) {
+; CHECK-LABEL: getSetCCResultType:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.wu $a1, $a0, 12
+; CHECK-NEXT: sltui $a1, $a1, 1
+; CHECK-NEXT: sub.d $a1, $zero, $a1
+; CHECK-NEXT: st.w $a1, $a0, 12
+; CHECK-NEXT: ld.wu $a1, $a0, 8
+; CHECK-NEXT: sltui $a1, $a1, 1
+; CHECK-NEXT: sub.d $a1, $zero, $a1
+; CHECK-NEXT: st.w $a1, $a0, 8
+; CHECK-NEXT: ld.wu $a1, $a0, 4
+; CHECK-NEXT: sltui $a1, $a1, 1
+; CHECK-NEXT: sub.d $a1, $zero, $a1
+; CHECK-NEXT: st.w $a1, $a0, 4
+; CHECK-NEXT: ld.wu $a1, $a0, 0
+; CHECK-NEXT: sltui $a1, $a1, 1
+; CHECK-NEXT: sub.d $a1, $zero, $a1
+; CHECK-NEXT: st.w $a1, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = load <4 x i32>, ptr %p, align 16
+ %cmp = icmp eq <4 x i32> %0, zeroinitializer
+ %sext = sext <4 x i1> %cmp to <4 x i32>
+ store <4 x i32> %sext, ptr %p, align 16
+ ret void
+}
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===================================================================
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -107,6 +107,9 @@
Value *Mask, Value *ShiftAmt,
AtomicOrdering Ord) const override;
+ EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+ EVT VT) const override;
+
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===================================================================
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -1860,6 +1860,14 @@
return false;
}
+EVT LoongArchTargetLowering::getSetCCResultType(const DataLayout &DL,
+ LLVMContext &Context,
+ EVT VT) const {
+ if (!VT.isVector())
+ return getPointerTy(DL);
+ return VT.changeVectorElementTypeToInteger();
+}
+
bool LoongArchTargetLowering::hasAndNot(SDValue Y) const {
// TODO: Support vectors.
return Y.getValueType().isScalarInteger() && !isa<ConstantSDNode>(Y);
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