[llvm] 68d4dbc - Revert "[InstCombine] fold exact sdiv to ashr"

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Sat Oct 8 07:02:32 PDT 2022


Author: Sanjay Patel
Date: 2022-10-08T10:02:03-04:00
New Revision: 68d4dbc2c17c8c0dd3e2563a82b53cb767bebc81

URL: https://github.com/llvm/llvm-project/commit/68d4dbc2c17c8c0dd3e2563a82b53cb767bebc81
DIFF: https://github.com/llvm/llvm-project/commit/68d4dbc2c17c8c0dd3e2563a82b53cb767bebc81.diff

LOG: Revert "[InstCombine] fold exact sdiv to ashr"

This reverts commit fe15290e0cf5d2bcdefca2e81ef6ff8155a2f7a8.
The test checks were not updated as expected.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
    llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index d9fcd436b00e0..69625c082c5c7 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -1199,11 +1199,6 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) {
       return BinaryOperator::CreateExactAShr(Op0, C);
     }
 
-    // sdiv exact X, (1<<ShAmt) --> ashr exact X, ShAmt (if shl is non-negative)
-    Value *ShAmt;
-    if (match(Op1, m_NSWShl(m_One(), m_Value(ShAmt))))
-      return BinaryOperator::CreateExactAShr(Op0, ShAmt);
-
     // sdiv exact X, -1<<C --> -(ashr exact X, C)
     if (match(Op1, m_NegatedPower2())) {
       Constant *NegPow2C = ConstantExpr::getNeg(cast<Constant>(Op1));

diff  --git a/llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll b/llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll
index ff650de2c5c80..8bc29d04118be 100644
--- a/llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll
+++ b/llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll
@@ -71,13 +71,16 @@ define <2 x i8> @n6_vec_negative(<2 x i8> %x) {
 }
 
 define i8 @shl1_nsw(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl1_nsw(
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw i8 1, [[Y:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv exact i8 [[X:%.*]], [[SHL]]
+; CHECK-NEXT:    ret i8 [[DIV]]
+;
   %shl = shl nsw i8 1, %y
   %div = sdiv exact i8 %x, %shl
   ret i8 %div
 }
 
-; negative test - must have nsw
-
 define i8 @shl1_nuw(i8 %x, i8 %y) {
 ; CHECK-LABEL: @shl1_nuw(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i8 1, [[Y:%.*]]
@@ -88,11 +91,3 @@ define i8 @shl1_nuw(i8 %x, i8 %y) {
   %div = sdiv exact i8 %x, %shl
   ret i8 %div
 }
-
-; negative test - must have exact
-
-define i8 @shl1_nsw_not_exact(i8 %x, i8 %y) {
-  %shl = shl nsw i8 1, %y
-  %div = sdiv i8 %x, %shl
-  ret i8 %div
-}


        


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