[PATCH] D135441: [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.

In D135441#3843605 <https://reviews.llvm.org/D135441#3843605>, @efriedma wrote:

> This is getting into the territory of actually being slower than a "mul", depending on the latency of "mul" and "add-with-shift" on the target CPU... we probably need CPU-specific modeling if you want to go this direction.

Thanks. As the Selection DAG doesn't include schedule model, so this should be checked in machine combiner?


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