[PATCH] D135448: [AArch64] Add SME 2 target feature for Armv8-A and Armv9-A 2022 Architecture Extension

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
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First patch in a series adding MC layer support for Scalable Matrix
Extension 2 (SME2).

This patch adds the following feature:

  sme2

The 2022 Architecture Extension release adds other feature flags(eg.:sme2.1),
that will be in follow-up patches.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135448

Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/test/MC/AArch64/SME2/feature.s


Index: llvm/test/MC/AArch64/SME2/feature.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME2/feature.s
@@ -0,0 +1,8 @@
+// This test verifies SME2 implies SME.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2  2>&1 < %s \
+// RUN:        | FileCheck %s
+
+addha   za0.s, p0/m, p0/m, z0.s
+// CHECK-NOT: instruction requires: sme
+// CHECK: addha   za0.s, p0/m, p0/m, z0.s
Index: llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -26,6 +26,7 @@
 
   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
                                                     PAUnsupported.F,
+                                                    SMEUnsupported.F,
                                                     [HasMTE]);
   // FIXME: Remove when all errors have been fixed.
   let FullInstRWOverlapCheck = 0;
Index: llvm/lib/Target/AArch64/AArch64SchedA64FX.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -22,7 +22,7 @@
 
   list<Predicate> UnsupportedFeatures =
     [HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
-     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16];
+     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2];
 
   let FullInstRWOverlapCheck = 0;
 }
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -142,6 +142,8 @@
                                  AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">;
 def HasSMEI64        : Predicate<"Subtarget->hasSMEI64()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">;
+def HasSME2          : Predicate<"Subtarget->hasSME2()">,
+                                 AssemblerPredicate<(all_of FeatureSME2), "sme2">;
 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
 // they should be enabled if either has been specified.
 def HasSVEorSME
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -473,6 +473,9 @@
 def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
   "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
 
+def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
+  "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
+
 def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
   "Apple A7 (the CPU formerly known as Cyclone)">;
 
@@ -642,7 +645,7 @@
 }
 
 def SMEUnsupported : AArch64Unsupported {
-  let F = [HasSME, HasSMEF64, HasSMEI64];
+  let F = [HasSME, HasSMEF64, HasSMEI64, HasSME2];
 }
 
 include "AArch64SchedA53.td"
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===================================================================
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -72,6 +72,7 @@
   AEK_HBC =         1ULL << 40, // FEAT_HBC
   AEK_MOPS =        1ULL << 41, // FEAT_MOPS
   AEK_PERFMON =     1ULL << 42, // FEAT_PMUv3
+  AEK_SME2 =        1ULL << 43, // FEAT_SME2
 };
 
 enum class ArchKind {
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===================================================================
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -146,6 +146,7 @@
 AARCH64_ARCH_EXT_NAME("sme",          AArch64::AEK_SME,         "+sme",          "-sme")
 AARCH64_ARCH_EXT_NAME("sme-f64",      AArch64::AEK_SMEF64,      "+sme-f64",      "-sme-f64")
 AARCH64_ARCH_EXT_NAME("sme-i64",      AArch64::AEK_SMEI64,      "+sme-i64",      "-sme-i64")
+AARCH64_ARCH_EXT_NAME("sme2",         AArch64::AEK_SME2,        "+sme2",         "-sme2")
 AARCH64_ARCH_EXT_NAME("hbc",          AArch64::AEK_HBC,         "+hbc",          "-hbc")
 AARCH64_ARCH_EXT_NAME("mops",         AArch64::AEK_MOPS,        "+mops",         "-mops")
 AARCH64_ARCH_EXT_NAME("pmuv3",        AArch64::AEK_PERFMON,     "+perfmon",      "-perfmon")


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