[PATCH] D132358: [RISCV][ISel] improved compressed instruction use

[Dmitry via Phabricator via llvm-commits]

dybv-sc added a comment.

Sorry for long silence.
I've benchmarked SPEC with llvm-test-suite on Alibaba THead machine and found out that there is slight performance downgrade with this substitution. I've isolated one case:

  lw      s0, 0(a0)
  li      a2, 101
  ld      a0, 0(a1)
  slliw   a1, s0, 1
  addw    a1, a1, s0
  sw      a1, 0(a0)
  blt     s0, a2, .LBB0_2

transforms to:

  lw      s0, 0(a0)
  ld      a0, 0(a1)
  slti    a2, s0, 101
  slliw   a1, s0, 1
  addw    a1, a1, s0
  sw      a1, 0(a0)
  bnez    a2, .LBB0_2

Being put in a hot loop the latter one adds 7 cycles more to each iteration. I found out that It does not affect branch predictor or cache, so there must be a pipeline stall happening here. I'll investigate this further.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D132358/new/

https://reviews.llvm.org/D132358