[PATCH] D135418: [VP][RISCV] Add vp.smax/smin/umax/umin intrinsics

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll:364
+
+; FIXME: The upper half is doing nothing.
+
----------------
eopXD wrote:
> Just to make sure, do you mean that LMUL should be m4 here?
I copied this from the vadd test. The VL is 128 so the upper half VL is zero as you can see in the vsetvli. But we don't strip any of the unneed code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135418/new/

https://reviews.llvm.org/D135418