[PATCH] D135316: [RISCV] Use branchless form for selects with -1 in either arm

[Philip Reames via Phabricator via llvm-commits]

reames updated this revision to Diff 465869.
reames added a comment.

Apply @craig.topper's suggestion - he was right about the effect.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135316/new/

https://reviews.llvm.org/D135316

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/min-max.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/uadd_sat.ll
  llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D135316.465869.patch
Type: text/x-patch
Size: 168850 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221006/25d94461/attachment-0001.bin>