[llvm] 8e3e962 - [ConstraintElimination] Order cmps for signed <-> unsigned transfer first.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2022-10-06T15:56:25+01:00
New Revision: 8e3e96298f5a205f6844b85fd0a6c21266140b12

URL: https://github.com/llvm/llvm-project/commit/8e3e96298f5a205f6844b85fd0a6c21266140b12
DIFF: https://github.com/llvm/llvm-project/commit/8e3e96298f5a205f6844b85fd0a6c21266140b12.diff

LOG: [ConstraintElimination] Order cmps for signed <-> unsigned transfer first.

Make sure conditions with constant operands come before conditions
without constant operands. This increases the effectiveness of the
current signed <-> unsigned fact transfer logic.

Added: 
    

Modified: 
    llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
    llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
    llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index a5513bc4f94d..b5329ac2658c 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -757,10 +757,20 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT) {
   // Next, sort worklist by dominance, so that dominating blocks and conditions
   // come before blocks and conditions dominated by them. If a block and a
   // condition have the same numbers, the condition comes before the block, as
-  // it holds on entry to the block.
-  stable_sort(S.WorkList, [](const ConstraintOrBlock &A, const ConstraintOrBlock &B) {
-    return std::tie(A.NumIn, A.IsBlock) < std::tie(B.NumIn, B.IsBlock);
-  });
+  // it holds on entry to the block. Also make sure conditions with constant
+  // operands come before conditions without constant operands. This increases
+  // the effectiveness of the current signed <-> unsigned fact transfer logic.
+  stable_sort(
+      S.WorkList, [](const ConstraintOrBlock &A, const ConstraintOrBlock &B) {
+        auto HasNoConstOp = [](const ConstraintOrBlock &B) {
+          return !B.IsBlock && !isa<ConstantInt>(B.Condition->getOperand(0)) &&
+                 !isa<ConstantInt>(B.Condition->getOperand(1));
+        };
+        bool NoConstOpA = HasNoConstOp(A);
+        bool NoConstOpB = HasNoConstOp(B);
+        return std::tie(A.NumIn, A.IsBlock, NoConstOpA) <
+               std::tie(B.NumIn, B.IsBlock, NoConstOpB);
+      });
 
   SmallVector<Instruction *> ToRemove;
 

diff  --git a/llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll b/llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
index 28f4aa8e5460..0a5cca92977d 100644
--- a/llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
+++ b/llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
@@ -53,7 +53,7 @@ define i1 @len_known_positive_via_idx_2(i8 %len, i8 %idx) {
 ; CHECK-NEXT:    [[T_2:%.*]] = icmp sge i8 [[LEN]], 0
 ; CHECK-NEXT:    [[C_1:%.*]] = icmp sge i8 [[LEN]], 2
 ; CHECK-NEXT:    [[C_2:%.*]] = icmp sge i8 [[LEN]], 2
-; CHECK-NEXT:    [[RES_1:%.*]] = xor i1 [[T_1]], true
+; CHECK-NEXT:    [[RES_1:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[RES_2:%.*]] = xor i1 [[RES_1]], [[C_1]]
 ; CHECK-NEXT:    [[RES_3:%.*]] = xor i1 [[RES_2]], [[C_2]]
 ; CHECK-NEXT:    ret i1 [[RES_3]]

diff  --git a/llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed.ll b/llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed.ll
index 913aab179981..fa0ea2616792 100644
--- a/llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed.ll
+++ b/llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed.ll
@@ -55,11 +55,11 @@ define i1 @idx_known_positive_via_len_2(i8 %len, i8 %idx) {
 ; CHECK:       then.1:
 ; CHECK-NEXT:    [[T_1:%.*]] = icmp ult i8 [[IDX]], [[LEN]]
 ; CHECK-NEXT:    [[T_2:%.*]] = icmp sge i8 [[IDX]], 0
-; CHECK-NEXT:    [[R_1:%.*]] = xor i1 true, [[T_2]]
+; CHECK-NEXT:    [[R_1:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[C_1:%.*]] = icmp sge i8 [[IDX]], 1
 ; CHECK-NEXT:    [[R_2:%.*]] = xor i1 [[R_1]], [[C_1]]
 ; CHECK-NEXT:    [[C_2:%.*]] = icmp sge i8 [[LEN]], 1
-; CHECK-NEXT:    [[R_3:%.*]] = xor i1 [[R_2]], [[C_2]]
+; CHECK-NEXT:    [[R_3:%.*]] = xor i1 [[R_2]], true
 ; CHECK-NEXT:    ret i1 [[R_3]]
 ; CHECK:       else:
 ; CHECK-NEXT:    [[C_3:%.*]] = icmp sge i8 [[IDX]], 0