[PATCH] D135316: [RISCV] Use branchless form for selects with -1 in either arm

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/uadd_sat_plus.ll:19
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a0, a0, -1
----------------
reames wrote:
> craig.topper wrote:
> > Is the seqz+addi equivalent to neg since a0 is [0,1]?
> It is.  Not sure what's causing this to be formed for RV32.  We get the not form for RV64.
> 
> (I literally just worked through the two cases by hand if you want to double check my reasoning.)
Sorry, typo.  We got the *neg* form for RV64.  


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  https://reviews.llvm.org/D135316/new/

https://reviews.llvm.org/D135316