[PATCH] D135316: [RISCV] Use branchless form for selects with -1 in either arm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9028
+      SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
+      SDValue Not =
+        DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), C);
----------------
Not -> Neg


================
Comment at: llvm/test/CodeGen/RISCV/uadd_sat_plus.ll:19
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a0, a0, -1
----------------
Is the seqz+addi equivalent to neg since a0 is [0,1]?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135316/new/

https://reviews.llvm.org/D135316