[PATCH] D135316: [RISCV] Use branchless form for selects with -1 in either arm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9034
+    if (isAllOnesConstant(FalseV)) {
+      SDValue C = DAG.getSetCC(DL, VT, RHS, LHS, CCVal);
+      SDValue Not =
----------------
Swapping operands is not the inverse.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135316/new/

https://reviews.llvm.org/D135316