[llvm] 203d0b0 - [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 5 08:15:55 PDT 2022
Author: Joe Nash
Date: 2022-10-05T11:15:40-04:00
New Revision: 203d0b0ee1369b1479da98922797ce68827fcd55
URL: https://github.com/llvm/llvm-project/commit/203d0b0ee1369b1479da98922797ce68827fcd55
DIFF: https://github.com/llvm/llvm-project/commit/203d0b0ee1369b1479da98922797ce68827fcd55.diff
LOG: [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.
For V_CMP_CLASS_F16_t16_e64 and V_CMPX_CLASS_F16_t16_e64,
https://reviews.llvm.org/D133723 changed the value type of src1 from i32 to i16.
These src1 operands are 16 bits, therefore need to be encoded as true16
operands. So the _e32 type was correctly set to VGPR_32_Lo128.
In _e64 form the operand class went from
VSrc_b32 to VSrc_b16. For some reason, we cannot encode inline literals for
VSrc_b16, see 5f5f566b265db00f577ead268400d99f34ba9cdd. In this phase of
the true16 implementation, VSrc_b16 and VSrc_b32 are still similar,
except from that quirk of inlines. So set the operand class to regain
that function.
Reviewed By: dp, arsenm
Differential Revision: https://reviews.llvm.org/D134897
Added:
Modified:
llvm/lib/Target/AMDGPU/VOPCInstructions.td
llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 13f5bed062dd..bc98b7322791 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -792,6 +792,7 @@ multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
def _t16 : VOPC_Class_Profile<sched, f16, i16> {
let IsTrue16 = 1;
let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
+ let Src1RC64 = VSrc_b32;
let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
@@ -819,6 +820,7 @@ multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
let IsTrue16 = 1;
let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>;
+ let Src1RC64 = VSrc_b32;
let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
index f535eff45d93..d333240d8a47 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
@@ -59,6 +59,10 @@ v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo
// W32: encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+v_cmp_class_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
v_cmp_class_f16_e64 s[10:11], v1, v2
// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
index ffc3a4c97647..bb3434a1bb15 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
@@ -46,6 +46,9 @@ v_cmpx_class_f16_e64 src_scc, vcc_lo
v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi
// GFX11: encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+v_cmpx_class_f16_e64 v1, 0.5
+// GFX11: encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+
v_cmpx_class_f32_e64 v1, v2
// GFX11: encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
index 3e6efcf26db8..8952c8c4aabd 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
@@ -5,6 +5,10 @@
# W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00
+# W32: v_cmp_class_f16_e64 s10, v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
+0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00
+
# W32: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
# W64: v_cmp_class_f16_e64 s[10:11], v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
index 3167013cc31f..d300bc4d2056 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt
@@ -4,6 +4,9 @@
# GFX11: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00
+# GFX11: v_cmpx_class_f16_e64 v1, 0.5 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00
+
# GFX11: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00
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