[PATCH] D135188: [RISCV][CodeGen] Add Scheduling for vset{i}vl{i} instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4453
+def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>,
+                     Sched<[WriteVSETIVLI, ReadVSETIVLI]>;
 }
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There's nothing to "Read" here. The sources are immediates


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135188/new/

https://reviews.llvm.org/D135188