[PATCH] D135194: [AArch64][NFC] Precommit test case to show sub-optimal codegen for add(lsl(val1,small-shift), lsl(val2,large-shift)).

[Mingming Liu via Phabricator via llvm-commits]

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Ideally, add operand with smaller shift should be RHS. In that way,
smaller-shift is folded into ADD.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135194

Files:
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll


Index: llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
===================================================================
--- llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -289,4 +289,16 @@
   ret void
 }
 
+define i64 @add_swap_rhs_lhs(i64 %0, i64 %1) {
+; CHECK-LABEL: add_swap_rhs_lhs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl x8, x1, #3
+; CHECK-NEXT:    add x0, x8, x0, lsl #8
+; CHECK-NEXT:    ret
+  %3 = shl i64 %0, 8
+  %4 = shl i64 %1, 3
+  %5 = add i64 %4, %3
+  ret i64 %5
+}
+
 !1 = !{!"branch_weights", i32 1, i32 1}


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