[llvm] cf43154 - [AArch64] Ensure condition (SUBS) has no uses of value in performCONDCombine

[David Green via llvm-commits]

Author: David Green
Date: 2022-10-04T21:18:30+01:00
New Revision: cf43154bc37540f32d0a345b7d5aa99d21f73cee

URL: https://github.com/llvm/llvm-project/commit/cf43154bc37540f32d0a345b7d5aa99d21f73cee
DIFF: https://github.com/llvm/llvm-project/commit/cf43154bc37540f32d0a345b7d5aa99d21f73cee.diff

LOG: [AArch64] Ensure condition (SUBS) has no uses of value in performCONDCombine

performCONDCombine removes and 0xff in patterns of
SUBS (and (add(..), 0xff), C)
under certain complex conditions. It doesn't come up often,
but in the lowering of usub.sat where the SUBS is both used as a
condition and as a value, the And is removed where it would only be
valid for the condition.

Fixes #58109.

Differential Revision: https://reviews.llvm.org/D135043

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/and-mask-removal.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 53df680f187d..2b3449bd303b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18760,7 +18760,7 @@ SDValue performCONDCombine(SDNode *N,
   SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
   unsigned CondOpcode = SubsNode->getOpcode();
 
-  if (CondOpcode != AArch64ISD::SUBS)
+  if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0))
     return SDValue();
 
   // There is a SUBS feeding this condition. Is it fed by a mask we can

diff  --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index 7ce8792766c8..d5b9ca253e8d 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -486,6 +486,7 @@ define i64 @pr58109(i8 signext %0) {
 ; CHECK-SD-LABEL: pr58109:
 ; CHECK-SD:       ; %bb.0:
 ; CHECK-SD-NEXT:    add w8, w0, #1
+; CHECK-SD-NEXT:    and w8, w8, #0xff
 ; CHECK-SD-NEXT:    subs w8, w8, #1
 ; CHECK-SD-NEXT:    csel w0, wzr, w8, lo
 ; CHECK-SD-NEXT:    ret