[PATCH] D133433: [AArch64-SVE]: lower masked load/store of 128-bit fixed-width vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1397
 
+    for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
+      if (useSVEForFixedLengthVectorVT(VT,
----------------
I think at some point we probably want to combine this with the code below:

    if (Subtarget->useSVEForFixedLengthVectors()) {
      for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
        if (useSVEForFixedLengthVectorVT(VT))
          addTypeForFixedLengthSVE(VT);

The problem is that `addTypeForFixedLengthSVE` will add a whole bunch of opcodes all at once, which we're probably not ready for.

@hassnaa-arm perhaps you can simplify this to something like:

  if (Subtarget->forceSVEInStreamingMode()) {
    for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
      if (useSVEForFixedLengthVectorVT(VT, true)
        addTypeForStreamingSVE(VT);
    for (MVT VT : MVT::fp_fixedlen_vector_valuetypes())
       if (useSVEForFixedLengthVectorVT(VT, true)
         addTypeForStreamingSVE(VT);
  }

where you add a function called `addTypeForStreamingSVE` a bit similar to `addTypeForFixedLengthSVE`. For now it would just be:

```void addTypeForStreamingSVE(EVT VT) {
  setOperationAction(ISD::ANY_EXTEND, VT, Custom);
  setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
  setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
  setOperationAction(ISD::LOAD, VT, Custom);
  setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
}```

What do you think?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133433/new/

https://reviews.llvm.org/D133433