[PATCH] D134418: [AMDGPU] Improve ISel for v_bfi instructions.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

I don't immediately see how shifts are relevant.

For the basic case of nested bitfield inserts, perhaps you could create tests for the cases you want to handle. For example, IR equivalents of:

1. (x & y) | (~x & z) // single insert
2. (x & y | (~x & ((u & v) | (~u & z))) // nested insert
3. (x & ((u & v) | (~u & y))) | (~x & z) // nested insert

For the nested inserts we might want separate test cases depending on whether the "select" arguments x and u are known to be disjoint or not. E.g. 0x0F and 0xF0 are disjoint, 0xFF0 and 0x0FF overlap, and for non-constant values we don't know whether they overlap or not.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134418/new/

https://reviews.llvm.org/D134418