[PATCH] D135122: [RISCV] Correct the setcc in vp.floor/ceil/round/roundeven lowering.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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We want to emit a masked setcc that preserves zeros in all of the bits
where the original mask is zero. To do this we need to pass the original
mask as the passthru operand as well. Otherwise, we'll use the mask agnostic
policy and replace the zeros with 1s on some CPUs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135122

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll

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