[PATCH] D135102: [AArch64] Combine or(and(val,shifted-mask), op) to or(shl(and(val>>N, mask), N), op)

[Mingming Liu via Phabricator via llvm-commits]

mingmingl created this revision.
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Result

1. The left-shift is unfolded into AArch64 ORR without added cost.
2. The AND operand is transformed without added cost, and chances are that the AND operand could be further simplified with its operand.

  Before: AND(val, shifted-mask)  # shifted-mask is a non-empty sequence of ones with N remainder zeros.

  After: AND(val >> N, mask)  # mask == (shifted-mask >> N), which is a bit-field-extraction instruction. bit-field-extraction has the same cost (latency, throughput, pipeline) as AND.

  When 'val' is a shift operation, chances are that transformed AND could be combined with this shift (see test cases)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135102

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-lsr-bfi.ll
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

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