[PATCH] D134783: [PowerPC] Fix a number of inefficiencies and issues with atomic code gen

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15754
+    };
+    // Combine branches fed by store conditional instructions (st[bhwd]cx).
+    unsigned StoreWidth = 0;
----------------
lkail wrote:
> Is it missing a test, kinda like
> ```
> define signext i1 @foo(i64* %addr, i64 %newval) {
> entry:
>   %0 = bitcast i64* %addr to i8*
>   br label %while.cond
> 
> while.cond:                                       ; preds = %while.body, %entry
>   %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %newval)
>   %ok = icmp eq i32 %1, 0
>   br i1 %ok, label %end, label %end.0
> end:
>   ret i1 0
> end.0:
>   ret i1 1
> }
> ```
We have it in `test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll` but I agree that it would probably be a good idea to add a simplified test case like this for each of the sizes. I'll add one for each of byte/halfword/word/doubleword.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134783/new/

https://reviews.llvm.org/D134783