[PATCH] D135078: [AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added a reviewer: paquette.
aemerson added a project: LLVM.
Herald added subscribers: hiraditya, kristof.beyls, rovka.
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aemerson requested review of this revision.

This fixes a long standing cause of awful code generation when legalization creates
G_SEXT(G_FCMP(...)), for example due to promoting the condition of a vector G_SELECT.

Since on AArch64 vector compares sign-extend the condition value, there's no need
for this extra G_SEXT. Unfortunately by the time we get to post-legalization these
G_SEXTs have already been lowered into shifts, so this combine is a bit more
involved than I'd ideally like. Oh well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135078

Files:
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sext-of-vcmp.mir
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/min-max.ll
  llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

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