[llvm] 1441d49 - [AArch64] Add pr58109 tests, one showing incorrect lowering of SUBS. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 3 07:08:55 PDT 2022
Author: David Green
Date: 2022-10-03T15:08:46+01:00
New Revision: 1441d49bb616b7f1111b44a395b092c5f17d6995
URL: https://github.com/llvm/llvm-project/commit/1441d49bb616b7f1111b44a395b092c5f17d6995
DIFF: https://github.com/llvm/llvm-project/commit/1441d49bb616b7f1111b44a395b092c5f17d6995.diff
LOG: [AArch64] Add pr58109 tests, one showing incorrect lowering of SUBS. NFC
Also added global-isel coverage for the same file.
Added:
Modified:
llvm/test/CodeGen/AArch64/and-mask-removal.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index bd88815a88d3b..7ce8792766c8a 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
@board = common global [400 x i8] zeroinitializer, align 1
@next_string = common global i32 0, align 4
@@ -7,25 +8,43 @@
; Function Attrs: nounwind ssp
define void @new_position(i32 %pos) {
-; CHECK-LABEL: new_position:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: adrp x9, _board at GOTPAGE
-; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: sxtw x8, w0
-; CHECK-NEXT: ldr x9, [x9, _board at GOTPAGEOFF]
-; CHECK-NEXT: ldrb w9, [x9, x8]
-; CHECK-NEXT: sub w9, w9, #1
-; CHECK-NEXT: cmp w9, #1
-; CHECK-NEXT: b.hi LBB0_2
-; CHECK-NEXT: ; %bb.1: ; %if.then
-; CHECK-NEXT: adrp x9, _next_string at GOTPAGE
-; CHECK-NEXT: adrp x10, _string_number at GOTPAGE
-; CHECK-NEXT: ldr x9, [x9, _next_string at GOTPAGEOFF]
-; CHECK-NEXT: ldr w9, [x9]
-; CHECK-NEXT: ldr x10, [x10, _string_number at GOTPAGEOFF]
-; CHECK-NEXT: str w9, [x10, x8, lsl #2]
-; CHECK-NEXT: LBB0_2: ; %if.end
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: new_position:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: adrp x9, _board at GOTPAGE
+; CHECK-SD-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: sxtw x8, w0
+; CHECK-SD-NEXT: ldr x9, [x9, _board at GOTPAGEOFF]
+; CHECK-SD-NEXT: ldrb w9, [x9, x8]
+; CHECK-SD-NEXT: sub w9, w9, #1
+; CHECK-SD-NEXT: cmp w9, #1
+; CHECK-SD-NEXT: b.hi LBB0_2
+; CHECK-SD-NEXT: ; %bb.1: ; %if.then
+; CHECK-SD-NEXT: adrp x9, _next_string at GOTPAGE
+; CHECK-SD-NEXT: adrp x10, _string_number at GOTPAGE
+; CHECK-SD-NEXT: ldr x9, [x9, _next_string at GOTPAGEOFF]
+; CHECK-SD-NEXT: ldr w9, [x9]
+; CHECK-SD-NEXT: ldr x10, [x10, _string_number at GOTPAGEOFF]
+; CHECK-SD-NEXT: str w9, [x10, x8, lsl #2]
+; CHECK-SD-NEXT: LBB0_2: ; %if.end
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: new_position:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: adrp x8, _board at GOTPAGE
+; CHECK-GI-NEXT: ldr x8, [x8, _board at GOTPAGEOFF]
+; CHECK-GI-NEXT: ldrb w8, [x8, w0, sxtw]
+; CHECK-GI-NEXT: sub w8, w8, #1
+; CHECK-GI-NEXT: cmp w8, #2
+; CHECK-GI-NEXT: b.hs LBB0_2
+; CHECK-GI-NEXT: ; %bb.1: ; %if.then
+; CHECK-GI-NEXT: adrp x8, _next_string at GOTPAGE
+; CHECK-GI-NEXT: adrp x9, _string_number at GOTPAGE
+; CHECK-GI-NEXT: ldr x8, [x8, _next_string at GOTPAGEOFF]
+; CHECK-GI-NEXT: ldr w8, [x8]
+; CHECK-GI-NEXT: ldr x9, [x9, _string_number at GOTPAGEOFF]
+; CHECK-GI-NEXT: str w8, [x9, w0, sxtw #2]
+; CHECK-GI-NEXT: LBB0_2: ; %if.end
+; CHECK-GI-NEXT: ret
entry:
%idxprom = sext i32 %pos to i64
%arrayidx = getelementptr inbounds [400 x i8], [400 x i8]* @board, i64 0, i64 %idxprom
@@ -63,12 +82,19 @@ ret_true:
}
define zeroext i1 @test8_1(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_1:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: sub w8, w0, #10
-; CHECK-NEXT: cmp w8, #89
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_1:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: sub w8, w0, #10
+; CHECK-SD-NEXT: cmp w8, #89
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_1:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #10
+; CHECK-GI-NEXT: cmp w8, #90
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, 246
%1 = icmp uge i8 %0, 90
@@ -80,11 +106,19 @@ ret_true:
}
define zeroext i1 @test8_2(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_2:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: cmp w0, #208
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_2:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: cmp w0, #208
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_2:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #29
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: cmp w8, #179
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, 227
%1 = icmp ne i8 %0, 179
@@ -96,11 +130,19 @@ ret_true:
}
define zeroext i1 @test8_3(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_3:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: cmp w0, #209
-; CHECK-NEXT: cset w0, eq
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_3:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: cmp w0, #209
+; CHECK-SD-NEXT: cset w0, eq
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_3:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #55
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: cmp w8, #154
+; CHECK-GI-NEXT: cset w0, eq
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, 201
%1 = icmp eq i8 %0, 154
@@ -112,11 +154,19 @@ ret_true:
}
define zeroext i1 @test8_4(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_4:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: cmp w0, #39
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_4:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: cmp w0, #39
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_4:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #79
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: cmp w8, #216
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, -79
%1 = icmp ne i8 %0, -40
@@ -128,12 +178,19 @@ ret_true:
}
define zeroext i1 @test8_5(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_5:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: sub w8, w0, #123
-; CHECK-NEXT: cmn w8, #106
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_5:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: sub w8, w0, #123
+; CHECK-SD-NEXT: cmn w8, #106
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_5:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #123
+; CHECK-GI-NEXT: cmn w8, #105
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, 133
%1 = icmp uge i8 %0, -105
@@ -145,12 +202,19 @@ ret_true:
}
define zeroext i1 @test8_6(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_6:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: sub w8, w0, #58
-; CHECK-NEXT: cmp w8, #154
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_6:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: sub w8, w0, #58
+; CHECK-SD-NEXT: cmp w8, #154
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_6:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #58
+; CHECK-GI-NEXT: cmp w8, #155
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, -58
%1 = icmp uge i8 %0, 155
@@ -181,11 +245,18 @@ ret_true:
define zeroext i1 @test8_8(i8 zeroext %x) align 2 {
-; CHECK-LABEL: test8_8:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: cmp w0, #66
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test8_8:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: cmp w0, #66
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test8_8:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub w8, w0, #66
+; CHECK-GI-NEXT: cmp w8, #1
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i8 %x, 190
%1 = icmp uge i8 %0, 1
@@ -197,12 +268,21 @@ ret_true:
}
define zeroext i1 @test16_0(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_0:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #5086
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_0:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #5086
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_0:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #18547
+; CHECK-GI-NEXT: mov w9, #23633
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, -46989
%1 = icmp ne i16 %0, -41903
@@ -214,14 +294,23 @@ ret_true:
}
define zeroext i1 @test16_2(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_2:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #16882
-; CHECK-NEXT: mov w9, #40700
-; CHECK-NEXT: add w8, w0, w8
-; CHECK-NEXT: cmp w9, w8, uxth
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_2:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #16882
+; CHECK-SD-NEXT: mov w9, #40700
+; CHECK-SD-NEXT: add w8, w0, w8
+; CHECK-SD-NEXT: cmp w9, w8, uxth
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_2:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #16882
+; CHECK-GI-NEXT: mov w9, #40699
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, 16882
%1 = icmp ule i16 %0, -24837
@@ -233,12 +322,21 @@ ret_true:
}
define zeroext i1 @test16_3(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_3:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #53200
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_3:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #53200
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_3:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #29283
+; CHECK-GI-NEXT: mov w9, #16947
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, 29283
%1 = icmp ne i16 %0, 16947
@@ -250,14 +348,23 @@ ret_true:
}
define zeroext i1 @test16_4(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_4:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #29985
-; CHECK-NEXT: mov w9, #15676
-; CHECK-NEXT: add w8, w0, w8
-; CHECK-NEXT: cmp w9, w8, uxth
-; CHECK-NEXT: cset w0, lo
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_4:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #29985
+; CHECK-SD-NEXT: mov w9, #15676
+; CHECK-SD-NEXT: add w8, w0, w8
+; CHECK-SD-NEXT: cmp w9, w8, uxth
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_4:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #29985
+; CHECK-GI-NEXT: mov w9, #15677
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, -35551
%1 = icmp uge i16 %0, 15677
@@ -269,12 +376,21 @@ ret_true:
}
define zeroext i1 @test16_5(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_5:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #23282
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_5:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #23282
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_5:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #-25214
+; CHECK-GI-NEXT: mov w9, #63604
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, -25214
%1 = icmp ne i16 %0, -1932
@@ -286,14 +402,23 @@ ret_true:
}
define zeroext i1 @test16_6(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_6:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #-32194
-; CHECK-NEXT: mov w9, #24320
-; CHECK-NEXT: add w8, w0, w8
-; CHECK-NEXT: cmp w8, w9
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_6:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #-32194
+; CHECK-SD-NEXT: mov w9, #24320
+; CHECK-SD-NEXT: add w8, w0, w8
+; CHECK-SD-NEXT: cmp w8, w9
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_6:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #-32194
+; CHECK-GI-NEXT: mov w9, #24321
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, -32194
%1 = icmp uge i16 %0, -41215
@@ -305,14 +430,23 @@ ret_true:
}
define zeroext i1 @test16_7(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_7:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #9272
-; CHECK-NEXT: mov w9, #22619
-; CHECK-NEXT: add w8, w0, w8
-; CHECK-NEXT: cmp w9, w8, uxth
-; CHECK-NEXT: cset w0, lo
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_7:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #9272
+; CHECK-SD-NEXT: mov w9, #22619
+; CHECK-SD-NEXT: add w8, w0, w8
+; CHECK-SD-NEXT: cmp w9, w8, uxth
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_7:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: mov w8, #9272
+; CHECK-GI-NEXT: mov w9, #22620
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, 9272
%1 = icmp uge i16 %0, -42916
@@ -324,12 +458,20 @@ ret_true:
}
define zeroext i1 @test16_8(i16 zeroext %x) align 2 {
-; CHECK-LABEL: test16_8:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov w8, #4919
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test16_8:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: mov w8, #4919
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test16_8:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: add w8, w0, #1787
+; CHECK-GI-NEXT: mov w9, #6706
+; CHECK-GI-NEXT: cmp w9, w8, uxth
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
entry:
%0 = add i16 %x, -63749
%1 = icmp ne i16 %0, 6706
@@ -340,3 +482,48 @@ ret_true:
ret i1 true
}
+define i64 @pr58109(i8 signext %0) {
+; CHECK-SD-LABEL: pr58109:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: add w8, w0, #1
+; CHECK-SD-NEXT: subs w8, w8, #1
+; CHECK-SD-NEXT: csel w0, wzr, w8, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: pr58109:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: add w8, w0, #1
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: sub w8, w8, #1
+; CHECK-GI-NEXT: cmp w8, w8, uxtb
+; CHECK-GI-NEXT: csel w8, wzr, w8, ne
+; CHECK-GI-NEXT: and x0, x8, #0xff
+; CHECK-GI-NEXT: ret
+ %2 = add i8 %0, 1
+ %3 = call i8 @llvm.usub.sat.i8(i8 %2, i8 1)
+ %4 = zext i8 %3 to i64
+ ret i64 %4
+}
+
+define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
+; CHECK-SD-LABEL: pr58109b:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: add w8, w0, #1
+; CHECK-SD-NEXT: cmp w8, #2
+; CHECK-SD-NEXT: csel x0, x1, x2, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: pr58109b:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: add w8, w0, #1
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: cmp w8, #2
+; CHECK-GI-NEXT: csel x0, x1, x2, lo
+; CHECK-GI-NEXT: ret
+ %2 = add i8 %0, 1
+ %3 = icmp ult i8 %2, 2
+ %4 = select i1 %3, i64 %a, i64 %b
+ ret i64 %4
+}
+
+declare i8 @llvm.usub.sat.i8(i8, i8) #0
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