[PATCH] D135059: [NFC][AArch64]Precommit test to show missed-optimization when the left-shift of a bit-field positioning could be folded into ORR

[Mingming Liu via Phabricator via llvm-commits]

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One operand of ORR is a bit-field positioning op [1]

[1] (AND (SHL (VAL, N), Shifted-Mask), Shifted-Mask is a non-empty sequence of
ones with remainder zero, and the number of zero is N.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135059

Files:
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll


Index: llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
===================================================================
--- llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -289,4 +289,58 @@
   ret void
 }
 
+define i64 @i64_or_lhs_bitfield_positioning(i64 %tmp1, i64 %tmp2) {
+; CHECK-LABEL: i64_or_lhs_bitfield_positioning:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w1, #7
+; CHECK-NEXT:    and x8, x8, #0x3f80
+; CHECK-NEXT:    orr x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %and = shl i64 %tmp2, 7
+  %shl = and i64 %and, 16256 ; 0x3f80
+  %or = or i64 %shl, %tmp1
+  ret i64 %or
+}
+
+define i64 @i64_or_rhs_bitfield_positioning(i64 %tmp1, i64 %tmp2) {
+; CHECK-LABEL: i64_or_rhs_bitfield_positioning:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w1, #7
+; CHECK-NEXT:    and x8, x8, #0x3f80
+; CHECK-NEXT:    orr x0, x0, x8
+; CHECK-NEXT:    ret
+entry:
+  %and = shl i64 %tmp2, 7
+  %shl = and i64 %and, 16256 ; 0x3f80
+  %or = or i64 %tmp1, %shl
+  ret i64 %or
+}
+
+define i32 @i32_or_lhs_bitfield_positioning(i32 %tmp1, i32 %tmp2) {
+; CHECK-LABEL: i32_or_lhs_bitfield_positioning:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ubfiz w8, w1, #7, #7
+; CHECK-NEXT:    orr w0, w8, w0
+; CHECK-NEXT:    ret
+entry:
+  %and = shl i32 %tmp2, 7
+  %shl = and i32 %and, 16256 ; 0x3f80
+  %or = or i32 %shl, %tmp1
+  ret i32 %or
+}
+
+define i32 @i32_or_rhs_bitfield_positioning(i32 %tmp1, i32 %tmp2) {
+; CHECK-LABEL: i32_or_rhs_bitfield_positioning:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ubfiz w8, w1, #7, #7
+; CHECK-NEXT:    orr w0, w0, w8
+; CHECK-NEXT:    ret
+entry:
+  %and = shl i32 %tmp2, 7
+  %shl = and i32 %and, 16256 ; 0x3f80
+  %or = or i32 %tmp1, %shl
+  ret i32 %or
+}
+
 !1 = !{!"branch_weights", i32 1, i32 1}


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