[PATCH] D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

AFAIK, the WWM register has some unmodeled liveness behavior, which makes it impossible to allocate wwm register together with normal vector register in one pass now.
For example(a typical if-then):

  bb0:
    %0 = ...
    s_cbranch_execz %bb2
  
  bb1:
    %1 = wwm_operation
    ... = %1
    %0 = implicit_def
  
  bb2:
    ... = %0

VGPR %0 was dead in `bb1` and WWM-VGPR %1 was defined and used in `bb1`. As there is no live-range conflict between them, they have a chance to get assigned the same physical register. If this happens, certain lane of %0 might be overwritten when writing to %1. I am not sure if moving the SIPreAllocateWWMRegs between the sgpr allocation and the vgpr allocation might help your case? The key point is to request the SIPreAllocateWWMRegs allocate the wwm register usage introduced in SILowerSGPRSpills.


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https://reviews.llvm.org/D124196