[llvm] 945a146 - [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr
Filipp Zhinkin via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 1 02:41:48 PDT 2022
Author: Filipp Zhinkin
Date: 2022-10-01T12:41:37+03:00
New Revision: 945a1468c922573a07b334a130d05f0ecca40926
URL: https://github.com/llvm/llvm-project/commit/945a1468c922573a07b334a130d05f0ecca40926
DIFF: https://github.com/llvm/llvm-project/commit/945a1468c922573a07b334a130d05f0ecca40926.diff
LOG: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr
Combine cmp with zero and all versions of AND, ORR, EOR and BIC instructions into S-suffixed versions.
Related issue: https://github.com/llvm/llvm-project/issues/57122
Reviewed By: efriedma, samtebbs
Differential Revision: https://reviews.llvm.org/D131786
Added:
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/test/CodeGen/ARM/branch-on-zero.ll
llvm/test/CodeGen/ARM/cmp-peephole.ll
llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/test/CodeGen/ARM/icmp-shift-opt.ll
llvm/test/CodeGen/ARM/sadd_sat.ll
llvm/test/CodeGen/ARM/sadd_sat_plus.ll
llvm/test/CodeGen/ARM/sat-to-bitop.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9f4025d6848f8..a5a5b73561547 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2979,20 +2979,38 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2SBCri:
case ARM::ANDrr:
case ARM::ANDri:
+ case ARM::ANDrsr:
+ case ARM::ANDrsi:
case ARM::t2ANDrr:
case ARM::t2ANDri:
+ case ARM::t2ANDrs:
case ARM::ORRrr:
case ARM::ORRri:
+ case ARM::ORRrsr:
+ case ARM::ORRrsi:
case ARM::t2ORRrr:
case ARM::t2ORRri:
+ case ARM::t2ORRrs:
case ARM::EORrr:
case ARM::EORri:
+ case ARM::EORrsr:
+ case ARM::EORrsi:
case ARM::t2EORrr:
case ARM::t2EORri:
+ case ARM::t2EORrs:
+ case ARM::BICri:
+ case ARM::BICrr:
+ case ARM::BICrsi:
+ case ARM::BICrsr:
+ case ARM::t2BICri:
+ case ARM::t2BICrr:
+ case ARM::t2BICrs:
case ARM::t2LSRri:
case ARM::t2LSRrr:
case ARM::t2LSLri:
case ARM::t2LSLrr:
+ case ARM::MOVsr:
+ case ARM::MOVsi:
return true;
}
}
@@ -3266,8 +3284,9 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
// Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
// set CPSR so this is represented as an explicit output)
if (!IsThumb1) {
- MI->getOperand(5).setReg(ARM::CPSR);
- MI->getOperand(5).setIsDef(true);
+ unsigned CPSRRegNum = MI->getNumExplicitOperands() - 1;
+ MI->getOperand(CPSRRegNum).setReg(ARM::CPSR);
+ MI->getOperand(CPSRRegNum).setIsDef(true);
}
assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
CmpInstr.eraseFromParent();
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 88bb74d1fc54b..9f014482063fb 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4891,6 +4891,13 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
(CMPrsi GPR:$src, so_reg_imm:$rhs)>;
def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
(CMPrsr GPR:$src, so_reg_reg:$rhs)>;
+// Following patterns aimed to prevent usage of CMPrsi and CMPrsr for a comparison
+// with zero. Usage of CMPri in these cases helps to replace cmp with S-versions of
+// shift instructions during peephole optimizations pass.
+def : ARMPat<(ARMcmpZ so_reg_imm:$rhs, 0),
+ (CMPri (MOVsi so_reg_imm:$rhs), 0)>;
+def : ARMPat<(ARMcmpZ so_reg_reg:$rhs, 0),
+ (CMPri (MOVsr so_reg_reg:$rhs), 0)>;
// CMN register-integer
let isCompare = 1, Defs = [CPSR] in {
diff --git a/llvm/test/CodeGen/ARM/branch-on-zero.ll b/llvm/test/CodeGen/ARM/branch-on-zero.ll
index 95bd71cdc7151..65fea323db0ca 100644
--- a/llvm/test/CodeGen/ARM/branch-on-zero.ll
+++ b/llvm/test/CodeGen/ARM/branch-on-zero.ll
@@ -56,19 +56,16 @@ define i32 @test_lshr(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
;
; CHECK-V7A-LABEL: test_lshr:
; CHECK-V7A: @ %bb.0: @ %entry
-; CHECK-V7A-NEXT: mov r3, #0
-; CHECK-V7A-NEXT: cmp r3, r2, lsr #2
-; CHECK-V7A-NEXT: beq .LBB0_3
-; CHECK-V7A-NEXT: @ %bb.1: @ %while.body.preheader
-; CHECK-V7A-NEXT: lsr r2, r2, #2
-; CHECK-V7A-NEXT: .LBB0_2: @ %while.body
+; CHECK-V7A-NEXT: lsrs r2, r2, #2
+; CHECK-V7A-NEXT: beq .LBB0_2
+; CHECK-V7A-NEXT: .LBB0_1: @ %while.body
; CHECK-V7A-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-V7A-NEXT: ldr r3, [r1], #4
; CHECK-V7A-NEXT: subs r2, r2, #1
; CHECK-V7A-NEXT: lsl r3, r3, #1
; CHECK-V7A-NEXT: str r3, [r0], #4
-; CHECK-V7A-NEXT: bne .LBB0_2
-; CHECK-V7A-NEXT: .LBB0_3: @ %while.end
+; CHECK-V7A-NEXT: bne .LBB0_1
+; CHECK-V7A-NEXT: .LBB0_2: @ %while.end
; CHECK-V7A-NEXT: mov r0, #0
; CHECK-V7A-NEXT: bx lr
entry:
@@ -145,19 +142,16 @@ define i32 @test_lshr2(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
;
; CHECK-V7A-LABEL: test_lshr2:
; CHECK-V7A: @ %bb.0: @ %entry
-; CHECK-V7A-NEXT: mov r3, #0
-; CHECK-V7A-NEXT: cmp r3, r2, lsr #2
-; CHECK-V7A-NEXT: beq .LBB1_3
-; CHECK-V7A-NEXT: @ %bb.1: @ %while.body.preheader
-; CHECK-V7A-NEXT: lsr r2, r2, #2
-; CHECK-V7A-NEXT: .LBB1_2: @ %while.body
+; CHECK-V7A-NEXT: lsrs r2, r2, #2
+; CHECK-V7A-NEXT: beq .LBB1_2
+; CHECK-V7A-NEXT: .LBB1_1: @ %while.body
; CHECK-V7A-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-V7A-NEXT: ldr r3, [r1], #4
; CHECK-V7A-NEXT: subs r2, r2, #1
; CHECK-V7A-NEXT: lsl r3, r3, #1
; CHECK-V7A-NEXT: str r3, [r0], #4
-; CHECK-V7A-NEXT: bne .LBB1_2
-; CHECK-V7A-NEXT: .LBB1_3: @ %while.end
+; CHECK-V7A-NEXT: bne .LBB1_1
+; CHECK-V7A-NEXT: .LBB1_2: @ %while.end
; CHECK-V7A-NEXT: mov r0, #0
; CHECK-V7A-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/ARM/cmp-peephole.ll b/llvm/test/CodeGen/ARM/cmp-peephole.ll
index 4cfbcef85929a..73888558e6647 100644
--- a/llvm/test/CodeGen/ARM/cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/cmp-peephole.ll
@@ -57,8 +57,7 @@ define i1 @cmp_ne_zero_and_ri(i32 %a) {
define i1 @cmp_ne_zero_and_rsr(i32 %a, i32 %b, i32 %c) {
; ARM-LABEL: cmp_ne_zero_and_rsr:
; ARM: @ %bb.0:
-; ARM-NEXT: and r0, r0, r1, lsl r2
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: ands r0, r0, r1, lsl r2
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -86,8 +85,7 @@ define i1 @cmp_ne_zero_and_rsr(i32 %a, i32 %b, i32 %c) {
define i1 @cmp_ne_zero_and_rsi(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_and_rsi:
; ARM: @ %bb.0:
-; ARM-NEXT: and r0, r0, r1, lsr #17
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: ands r0, r0, r1, lsr #17
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -101,8 +99,7 @@ define i1 @cmp_ne_zero_and_rsi(i32 %a, i32 %b) {
;
; THUMB2-LABEL: cmp_ne_zero_and_rsi:
; THUMB2: @ %bb.0:
-; THUMB2-NEXT: and.w r0, r0, r1, lsr #17
-; THUMB2-NEXT: cmp r0, #0
+; THUMB2-NEXT: ands.w r0, r0, r1, lsr #17
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -166,8 +163,7 @@ define i1 @cmp_ne_zero_or_ri(i32 %a) {
define i1 @cmp_ne_zero_or_rsr(i32 %a, i32 %b, i32 %c) {
; ARM-LABEL: cmp_ne_zero_or_rsr:
; ARM: @ %bb.0:
-; ARM-NEXT: orr r0, r0, r1, lsl r2
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: orrs r0, r0, r1, lsl r2
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -195,8 +191,7 @@ define i1 @cmp_ne_zero_or_rsr(i32 %a, i32 %b, i32 %c) {
define i1 @cmp_ne_zero_or_rsi(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_or_rsi:
; ARM: @ %bb.0:
-; ARM-NEXT: orr r0, r0, r1, lsr #17
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: orrs r0, r0, r1, lsr #17
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -210,8 +205,7 @@ define i1 @cmp_ne_zero_or_rsi(i32 %a, i32 %b) {
;
; THUMB2-LABEL: cmp_ne_zero_or_rsi:
; THUMB2: @ %bb.0:
-; THUMB2-NEXT: orr.w r0, r0, r1, lsr #17
-; THUMB2-NEXT: cmp r0, #0
+; THUMB2-NEXT: orrs.w r0, r0, r1, lsr #17
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -274,8 +268,7 @@ define i1 @cmp_ne_zero_xor_ri(i32 %a) {
define i1 @cmp_ne_zero_xor_rsr(i32 %a, i32 %b, i32 %c) {
; ARM-LABEL: cmp_ne_zero_xor_rsr:
; ARM: @ %bb.0:
-; ARM-NEXT: eor r0, r0, r1, lsl r2
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: eors r0, r0, r1, lsl r2
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -303,8 +296,7 @@ define i1 @cmp_ne_zero_xor_rsr(i32 %a, i32 %b, i32 %c) {
define i1 @cmp_ne_zero_xor_rsi(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_xor_rsi:
; ARM: @ %bb.0:
-; ARM-NEXT: eor r0, r0, r1, lsr #17
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: eors r0, r0, r1, lsr #17
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -318,8 +310,7 @@ define i1 @cmp_ne_zero_xor_rsi(i32 %a, i32 %b) {
;
; THUMB2-LABEL: cmp_ne_zero_xor_rsi:
; THUMB2: @ %bb.0:
-; THUMB2-NEXT: eor.w r0, r0, r1, lsr #17
-; THUMB2-NEXT: cmp r0, #0
+; THUMB2-NEXT: eors.w r0, r0, r1, lsr #17
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -332,8 +323,7 @@ define i1 @cmp_ne_zero_xor_rsi(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_and_not_rr(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_and_not_rr:
; ARM: @ %bb.0:
-; ARM-NEXT: bic r0, r0, r1
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: bics r0, r0, r1
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -347,7 +337,6 @@ define i1 @cmp_ne_zero_and_not_rr(i32 %a, i32 %b) {
; THUMB2-LABEL: cmp_ne_zero_and_not_rr:
; THUMB2: @ %bb.0:
; THUMB2-NEXT: bics r0, r1
-; THUMB2-NEXT: cmp r0, #0
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -360,8 +349,7 @@ define i1 @cmp_ne_zero_and_not_rr(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_and_not_ri(i32 %a) {
; ARM-LABEL: cmp_ne_zero_and_not_ri:
; ARM: @ %bb.0:
-; ARM-NEXT: bic r0, r0, #42
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: bics r0, r0, #42
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -375,8 +363,7 @@ define i1 @cmp_ne_zero_and_not_ri(i32 %a) {
;
; THUMB2-LABEL: cmp_ne_zero_and_not_ri:
; THUMB2: @ %bb.0:
-; THUMB2-NEXT: bic r0, r0, #42
-; THUMB2-NEXT: cmp r0, #0
+; THUMB2-NEXT: bics r0, r0, #42
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -389,8 +376,7 @@ define i1 @cmp_ne_zero_and_not_ri(i32 %a) {
define i1 @cmp_ne_zero_and_not_rsr(i32 %a, i32 %b, i32 %c) {
; ARM-LABEL: cmp_ne_zero_and_not_rsr:
; ARM: @ %bb.0:
-; ARM-NEXT: bic r0, r0, r1, lsl r2
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: bics r0, r0, r1, lsl r2
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -406,7 +392,6 @@ define i1 @cmp_ne_zero_and_not_rsr(i32 %a, i32 %b, i32 %c) {
; THUMB2: @ %bb.0:
; THUMB2-NEXT: lsls r1, r2
; THUMB2-NEXT: bics r0, r1
-; THUMB2-NEXT: cmp r0, #0
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -420,8 +405,7 @@ define i1 @cmp_ne_zero_and_not_rsr(i32 %a, i32 %b, i32 %c) {
define i1 @cmp_ne_zero_and_not_rsi(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_and_not_rsi:
; ARM: @ %bb.0:
-; ARM-NEXT: bic r0, r0, r1, lsr #17
-; ARM-NEXT: cmp r0, #0
+; ARM-NEXT: bics r0, r0, r1, lsr #17
; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
@@ -435,8 +419,7 @@ define i1 @cmp_ne_zero_and_not_rsi(i32 %a, i32 %b) {
;
; THUMB2-LABEL: cmp_ne_zero_and_not_rsi:
; THUMB2: @ %bb.0:
-; THUMB2-NEXT: bic.w r0, r0, r1, lsr #17
-; THUMB2-NEXT: cmp r0, #0
+; THUMB2-NEXT: bics.w r0, r0, r1, lsr #17
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne r0, #1
; THUMB2-NEXT: bx lr
@@ -450,11 +433,8 @@ define i1 @cmp_ne_zero_and_not_rsi(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_shl_rr(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_shl_rr:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r3, #0
-; ARM-NEXT: lsl r2, r0, r1
-; ARM-NEXT: cmp r3, r0, lsl r1
-; ARM-NEXT: movwne r2, #1
-; ARM-NEXT: mov r0, r2
+; ARM-NEXT: lsls r0, r0, r1
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_shl_rr:
@@ -478,11 +458,8 @@ define i1 @cmp_ne_zero_shl_rr(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_shl_ri(i32 %a) {
; ARM-LABEL: cmp_ne_zero_shl_ri:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r2, #0
-; ARM-NEXT: lsl r1, r0, #7
-; ARM-NEXT: cmp r2, r0, lsl #7
-; ARM-NEXT: movwne r1, #1
-; ARM-NEXT: mov r0, r1
+; ARM-NEXT: lsls r0, r0, #7
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_shl_ri:
@@ -506,11 +483,8 @@ define i1 @cmp_ne_zero_shl_ri(i32 %a) {
define i1 @cmp_ne_zero_lshr_rr(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_lshr_rr:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r3, #0
-; ARM-NEXT: lsr r2, r0, r1
-; ARM-NEXT: cmp r3, r0, lsr r1
-; ARM-NEXT: movwne r2, #1
-; ARM-NEXT: mov r0, r2
+; ARM-NEXT: lsrs r0, r0, r1
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_lshr_rr:
@@ -534,11 +508,8 @@ define i1 @cmp_ne_zero_lshr_rr(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_lshr_ri(i32 %a) {
; ARM-LABEL: cmp_ne_zero_lshr_ri:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r2, #0
-; ARM-NEXT: lsr r1, r0, #7
-; ARM-NEXT: cmp r2, r0, lsr #7
-; ARM-NEXT: movwne r1, #1
-; ARM-NEXT: mov r0, r1
+; ARM-NEXT: lsrs r0, r0, #7
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_lshr_ri:
@@ -562,11 +533,8 @@ define i1 @cmp_ne_zero_lshr_ri(i32 %a) {
define i1 @cmp_ne_zero_ashr_rr(i32 %a, i32 %b) {
; ARM-LABEL: cmp_ne_zero_ashr_rr:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r3, #0
-; ARM-NEXT: asr r2, r0, r1
-; ARM-NEXT: cmp r3, r0, asr r1
-; ARM-NEXT: movwne r2, #1
-; ARM-NEXT: mov r0, r2
+; ARM-NEXT: asrs r0, r0, r1
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_ashr_rr:
@@ -591,11 +559,8 @@ define i1 @cmp_ne_zero_ashr_rr(i32 %a, i32 %b) {
define i1 @cmp_ne_zero_ashr_ri(i32 %a) {
; ARM-LABEL: cmp_ne_zero_ashr_ri:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r2, #0
-; ARM-NEXT: asr r1, r0, #7
-; ARM-NEXT: cmp r2, r0, asr #7
-; ARM-NEXT: movwne r1, #1
-; ARM-NEXT: mov r0, r1
+; ARM-NEXT: asrs r0, r0, #7
+; ARM-NEXT: movwne r0, #1
; ARM-NEXT: bx lr
;
; THUMB-LABEL: cmp_ne_zero_ashr_ri:
@@ -1520,8 +1485,7 @@ exit:
define void @br_on_shift_eq_zero(i32 %a, i32 %b) {
; ARM-LABEL: br_on_shift_eq_zero:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r2, #0
-; ARM-NEXT: cmp r2, r0, lsl r1
+; ARM-NEXT: lsls r1, r0, r1
; ARM-NEXT: bxne lr
; ARM-NEXT: .LBB51_1: @ %true_br
; ARM-NEXT: push {r11, lr}
@@ -1564,8 +1528,7 @@ exit:
define void @br_on_shift_ne_zero(i32 %a, i32 %b) {
; ARM-LABEL: br_on_shift_ne_zero:
; ARM: @ %bb.0:
-; ARM-NEXT: mov r2, #0
-; ARM-NEXT: cmp r2, r0, lsr r1
+; ARM-NEXT: lsrs r1, r0, r1
; ARM-NEXT: bxeq lr
; ARM-NEXT: .LBB52_1: @ %true_br
; ARM-NEXT: push {r11, lr}
diff --git a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
index ef1d61dc66311..16b7403bdb932 100644
--- a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
+++ b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
@@ -630,20 +630,17 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: ldrd lr, r0, [sp, #8]
; CHECKV7M-NEXT: beq .LBB6_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
-; CHECKV7M-NEXT: orr.w r2, r3, r2, lsr #17
-; CHECKV7M-NEXT: orr.w r1, r1, r12, lsr #17
-; CHECKV7M-NEXT: cmp r2, #0
+; CHECKV7M-NEXT: orrs.w r2, r3, r2, lsr #17
; CHECKV7M-NEXT: mov r2, r0
; CHECKV7M-NEXT: it ne
; CHECKV7M-NEXT: movne r2, lr
-; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: orrs.w r1, r1, r12, lsr #17
; CHECKV7M-NEXT: it ne
; CHECKV7M-NEXT: movne r0, lr
; CHECKV7M-NEXT: add r0, r2
; CHECKV7M-NEXT: pop {r7, pc}
; CHECKV7M-NEXT: .LBB6_2: @ %else
-; CHECKV7M-NEXT: orr.w r1, r3, r2, lsr #17
-; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: orrs.w r1, r3, r2, lsr #17
; CHECKV7M-NEXT: it ne
; CHECKV7M-NEXT: movne r0, lr
; CHECKV7M-NEXT: pop {r7, pc}
@@ -658,20 +655,17 @@ define i32 @icmp64_uge_m2(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r4, r4, #31
; CHECKV7A-NEXT: beq .LBB6_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
-; CHECKV7A-NEXT: orr.w r2, r3, r2, lsr #17
-; CHECKV7A-NEXT: orr.w r1, r1, r12, lsr #17
-; CHECKV7A-NEXT: cmp r2, #0
+; CHECKV7A-NEXT: orrs.w r2, r3, r2, lsr #17
; CHECKV7A-NEXT: mov r2, r0
; CHECKV7A-NEXT: it ne
; CHECKV7A-NEXT: movne r2, lr
-; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: orrs.w r1, r1, r12, lsr #17
; CHECKV7A-NEXT: it ne
; CHECKV7A-NEXT: movne r0, lr
; CHECKV7A-NEXT: add r0, r2
; CHECKV7A-NEXT: pop {r4, pc}
; CHECKV7A-NEXT: .LBB6_2: @ %else
-; CHECKV7A-NEXT: orr.w r1, r3, r2, lsr #17
-; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: orrs.w r1, r3, r2, lsr #17
; CHECKV7A-NEXT: it ne
; CHECKV7A-NEXT: movne r0, lr
; CHECKV7A-NEXT: pop {r4, pc}
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 21fdfd863bed7..7cc623fb0a616 100644
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -970,9 +970,8 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
; ARM6: @ %bb.0:
; ARM6-NEXT: uxtb r1, r1
; ARM6-NEXT: mov r2, #24
-; ARM6-NEXT: and r1, r0, r2, lsr r1
+; ARM6-NEXT: ands r0, r0, r2, lsr r1
; ARM6-NEXT: mov r0, #0
-; ARM6-NEXT: cmp r1, #0
; ARM6-NEXT: movmi r0, #1
; ARM6-NEXT: bx lr
;
@@ -980,9 +979,8 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
; ARM78: @ %bb.0:
; ARM78-NEXT: uxtb r1, r1
; ARM78-NEXT: mov r2, #24
-; ARM78-NEXT: and r1, r0, r2, lsr r1
+; ARM78-NEXT: ands r0, r0, r2, lsr r1
; ARM78-NEXT: mov r0, #0
-; ARM78-NEXT: cmp r1, #0
; ARM78-NEXT: movwmi r0, #1
; ARM78-NEXT: bx lr
;
diff --git a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
index b51eb846f24b3..c5fd16a461582 100644
--- a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
+++ b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
@@ -12,8 +12,7 @@ define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind {
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: adds r0, r0, #1
; CHECK-NEXT: adc r1, r1, #0
-; CHECK-NEXT: orr r2, r1, r0, lsr #16
-; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: orrs r2, r1, r0, lsr #16
; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %exit
; CHECK-NEXT: bx lr
@@ -44,8 +43,7 @@ define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind {
define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {
; CHECK-LABEL: opt_setcc_srl_ne_zero:
; CHECK: @ %bb.0:
-; CHECK-NEXT: orr r0, r1, r0, lsr #17
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: orrs r0, r1, r0, lsr #17
; CHECK-NEXT: movwne r0, #1
; CHECK-NEXT: bx lr
%srl = lshr i64 %a, 17
@@ -68,8 +66,7 @@ define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind {
define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind {
; CHECK-LABEL: opt_setcc_shl_ne_zero:
; CHECK: @ %bb.0:
-; CHECK-NEXT: orr r0, r0, r1, lsl #17
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: orrs r0, r0, r1, lsl #17
; CHECK-NEXT: movwne r0, #1
; CHECK-NEXT: bx lr
%shl = shl i64 %a, 17
@@ -144,8 +141,7 @@ define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind {
; CHECK-NEXT: orr r2, r0, r3
; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: lsr r0, r0, #15
-; CHECK-NEXT: orr r0, r0, r2, lsl #17
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: orrs r0, r0, r2, lsl #17
; CHECK-NEXT: movwne r0, #1
; CHECK-NEXT: bx lr
%shl = shl i128 %a, 17
diff --git a/llvm/test/CodeGen/ARM/sadd_sat.ll b/llvm/test/CodeGen/ARM/sadd_sat.ll
index e0aca8e433805..fc9cd2d5ef5b5 100644
--- a/llvm/test/CodeGen/ARM/sadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat.ll
@@ -94,11 +94,10 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T2-NEXT: eor.w r12, r1, r3
; CHECK-T2-NEXT: adc.w r2, r1, r3
; CHECK-T2-NEXT: eors r1, r2
-; CHECK-T2-NEXT: bic.w r1, r1, r12
-; CHECK-T2-NEXT: cmp r1, #0
-; CHECK-T2-NEXT: mov.w r1, #-2147483648
+; CHECK-T2-NEXT: bics.w r1, r1, r12
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: asrmi r0, r2, #31
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
; CHECK-T2-NEXT: mov r1, r2
@@ -110,10 +109,9 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-ARM-NEXT: eor r12, r1, r3
; CHECK-ARM-NEXT: adc r2, r1, r3
; CHECK-ARM-NEXT: eor r1, r1, r2
-; CHECK-ARM-NEXT: bic r1, r1, r12
-; CHECK-ARM-NEXT: cmp r1, #0
-; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: bics r1, r1, r12
; CHECK-ARM-NEXT: asrmi r0, r2, #31
+; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
; CHECK-ARM-NEXT: mov r1, r2
; CHECK-ARM-NEXT: bx lr
diff --git a/llvm/test/CodeGen/ARM/sadd_sat_plus.ll b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
index bbdfa6cea6e47..859aedc7a3f01 100644
--- a/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
@@ -91,10 +91,9 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T2-NEXT: eor.w r3, r1, r12
; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: bics r1, r3
-; CHECK-T2-NEXT: cmp r1, #0
-; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: asrmi r0, r2, #31
+; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
; CHECK-T2-NEXT: mov r1, r2
@@ -108,10 +107,9 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-ARM-NEXT: eor r3, r1, r2
; CHECK-ARM-NEXT: adc r2, r1, r2
; CHECK-ARM-NEXT: eor r1, r1, r2
-; CHECK-ARM-NEXT: bic r1, r1, r3
-; CHECK-ARM-NEXT: cmp r1, #0
-; CHECK-ARM-NEXT: mov r1, #-2147483648
+; CHECK-ARM-NEXT: bics r1, r1, r3
; CHECK-ARM-NEXT: asrmi r0, r2, #31
+; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
; CHECK-ARM-NEXT: mov r1, r2
; CHECK-ARM-NEXT: bx lr
diff --git a/llvm/test/CodeGen/ARM/sat-to-bitop.ll b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
index 63d2d929d76a2..dcd396749ce57 100644
--- a/llvm/test/CodeGen/ARM/sat-to-bitop.ll
+++ b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
@@ -37,8 +37,7 @@ define i16 @sat0_base_16bit(i16 %x) #0 {
; CHECK-ARM-LABEL: sat0_base_16bit:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: lsl r1, r0, #16
-; CHECK-ARM-NEXT: asr r1, r1, #16
-; CHECK-ARM-NEXT: cmp r1, #0
+; CHECK-ARM-NEXT: asrs r1, r1, #16
; CHECK-ARM-NEXT: movmi r0, #0
; CHECK-ARM-NEXT: mov pc, lr
;
@@ -71,8 +70,7 @@ define i8 @sat0_base_8bit(i8 %x) #0 {
; CHECK-ARM-LABEL: sat0_base_8bit:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: lsl r1, r0, #24
-; CHECK-ARM-NEXT: asr r1, r1, #24
-; CHECK-ARM-NEXT: cmp r1, #0
+; CHECK-ARM-NEXT: asrs r1, r1, #24
; CHECK-ARM-NEXT: movmi r0, #0
; CHECK-ARM-NEXT: mov pc, lr
;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
index ab95baeedf610..dcb57a5ea6afd 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
@@ -39,10 +39,10 @@ define void @arm_cmplx_dot_prod_f32(float* %pSrcA, float* %pSrcB, i32 %numSample
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #90
; CHECK-NEXT: vldrw.u32 q1, [r1, #-16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #-16]
-; CHECK-NEXT: and.w r2, r4, r2, lsl #1
+; CHECK-NEXT: ands.w r2, r4, r2, lsl #1
; CHECK-NEXT: vcmla.f32 q0, q2, q1, #0
; CHECK-NEXT: vcmla.f32 q0, q2, q1, #90
-; CHECK-NEXT: cbz r2, .LBB0_8
+; CHECK-NEXT: beq .LBB0_8
; CHECK-NEXT: @ %bb.4: @ %while.body9
; CHECK-NEXT: vctp.32 r2
; CHECK-NEXT: cmp r2, #4
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
index 86229880e480d..04d0b46dea67b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
@@ -335,39 +335,36 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov r10, s8
; CHECK-NEXT: vmov.f32 s8, s6
-; CHECK-NEXT: vmov r6, s2
+; CHECK-NEXT: vmov r7, s2
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: asr.w r0, r10, #31
-; CHECK-NEXT: asrs r7, r6, #31
+; CHECK-NEXT: asrs r5, r7, #31
; CHECK-NEXT: adds.w r4, r10, r2
+; CHECK-NEXT: eor.w r6, r10, r2
; CHECK-NEXT: adc r3, r0, #0
; CHECK-NEXT: asrl r4, r3, r2
; CHECK-NEXT: subs r0, r4, r2
; CHECK-NEXT: sbc lr, r3, #0
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: umull r0, r8, r0, r2
-; CHECK-NEXT: adds r4, r6, r3
-; CHECK-NEXT: eor.w r1, r6, r3
-; CHECK-NEXT: adc r5, r7, #0
-; CHECK-NEXT: eor.w r7, r10, r2
+; CHECK-NEXT: adds r4, r7, r3
+; CHECK-NEXT: eor.w r1, r7, r3
+; CHECK-NEXT: adc r5, r5, #0
; CHECK-NEXT: asrl r4, r5, r3
-; CHECK-NEXT: orr.w r7, r7, r10, asr #31
; CHECK-NEXT: subs r4, r4, r3
-; CHECK-NEXT: orr.w r1, r1, r6, asr #31
; CHECK-NEXT: sbc r5, r5, #0
-; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: orrs.w r6, r6, r10, asr #31
; CHECK-NEXT: umull r4, r12, r4, r3
; CHECK-NEXT: csetm r9, eq
-; CHECK-NEXT: movs r7, #0
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: bfi r7, r9, #0, #8
+; CHECK-NEXT: orrs.w r1, r1, r7, asr #31
+; CHECK-NEXT: mov.w r6, #0
; CHECK-NEXT: csetm r1, eq
-; CHECK-NEXT: bfi r7, r1, #8, #8
+; CHECK-NEXT: bfi r6, r9, #0, #8
; CHECK-NEXT: mla r5, r5, r3, r12
-; CHECK-NEXT: rsbs r1, r6, #0
-; CHECK-NEXT: vmsr p0, r7
+; CHECK-NEXT: bfi r6, r1, #8, #8
+; CHECK-NEXT: rsbs r1, r7, #0
; CHECK-NEXT: mla r7, lr, r2, r8
; CHECK-NEXT: lsll r4, r5, r1
; CHECK-NEXT: rsb.w r1, r10, #0
@@ -376,8 +373,9 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: lsll r0, r7, r2
; CHECK-NEXT: lsll r4, r5, r3
-; CHECK-NEXT: mov.w r12, #0
+; CHECK-NEXT: vmsr p0, r6
; CHECK-NEXT: vmov q3[2], q3[0], r0, r4
+; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vpsel q2, q3, q2
; CHECK-NEXT: adds.w r2, lr, r1
; CHECK-NEXT: asr.w r0, lr, #31
@@ -396,12 +394,10 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: sbc r8, r5, #0
; CHECK-NEXT: mla r5, r7, r1, r6
; CHECK-NEXT: eor.w r6, lr, r1
-; CHECK-NEXT: orr.w r6, r6, lr, asr #31
+; CHECK-NEXT: orrs.w r6, r6, lr, asr #31
; CHECK-NEXT: eor.w r7, r2, r3
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: orr.w r7, r7, r2, asr #31
; CHECK-NEXT: csetm r6, eq
-; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: orrs.w r7, r7, r2, asr #31
; CHECK-NEXT: csetm r7, eq
; CHECK-NEXT: rsb.w lr, lr, #0
; CHECK-NEXT: bfi r12, r7, #0, #8
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