[PATCH] D135009: [RISCV] Refactor and improve eliminateFrameIndex.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 30 20:00:13 PDT 2022


craig.topper created this revision.
craig.topper added reviewers: reames, frasercrmck, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

There are few changes mixed in here.

-Try to reuse the destination register from ADDI instead of always
creating a virtual register. This way we lean on the register
scavenger in fewer case.
-Explicitly reuse the primary virtual register when possible. There's
still a case where both getVLENFactoredAmount and handling large
fixed offsets can both create a secondary virtual register.
-Combine similar BuildMI calls by manipulating the Register variables.

There are still a couple early outs for ADDI, but overall I tried to
arrange the code into steps.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135009

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D135009.464460.patch
Type: text/x-patch
Size: 15401 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221001/6a4883d2/attachment.bin>


More information about the llvm-commits mailing list